Issued Patents All Time
Showing 25 most recent of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8190391 | Determining die performance by incorporating neighboring die performance metrics | Gregory A. Cherry, Carl Bowen, Luis De La Fuente, Rajesh Vijayaraghavan | 2012-05-29 |
| 7650199 | End of line performance prediction | — | 2010-01-19 |
| 7315765 | Automated control thread determination based upon post-process consideration | Alan Grosvenor Ranft | 2008-01-01 |
| 7248939 | Method and apparatus for multivariate fault detection and classification | Kevin Andrew Chamness, Gregory A. Cherry, Jason Williams | 2007-07-24 |
| 7198964 | Method and apparatus for detecting faults using principal component analysis parameter groupings | Gregory A. Cherry | 2007-04-03 |
| 6949436 | Composite spacer liner for improved transistor performance | James F. Buller, David Wu, Scott Luning, Derick J. Wristers | 2005-09-27 |
| 6777281 | Maintaining LDD series resistance of MOS transistors by retarding dopant segregation | Scott Luning, Akif Sultan, David Wu | 2004-08-17 |
| 6764908 | Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents | Derick J. Wristers, Qi Xiang, Bin Yu | 2004-07-20 |
| 6720227 | Method of forming source/drain regions in a semiconductor device | Jon D. Cheek, James F. Buller, Basab Bandyopadhyay | 2004-04-13 |
| 6589847 | Tilted counter-doped implant to sharpen halo profile | Scott Luning, Derick J. Wristers | 2003-07-08 |
| 6506642 | Removable spacer technique | Scott Luning, Jon D. Cheek, James F. Buller, David E. Brown | 2003-01-14 |
| 6504218 | Asymmetrical N-channel and P-channel devices | Mark I. Gardner | 2003-01-07 |
| 6420730 | Elevated transistor fabrication technique | Mark I. Gardner, Michael Duane | 2002-07-16 |
| 6403979 | Test structure for measuring effective channel length of a transistor | Jon D. Cheek | 2002-06-11 |
| 6383872 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure | Mark I. Gardner, Jon D. Cheek | 2002-05-07 |
| 6365943 | High density integrated circuit | Mark I. Gardner, Fred N. Hause | 2002-04-02 |
| 6358828 | Ultra high density series-connected transistors formed on separate elevational levels | Mark I. Gardner | 2002-03-19 |
| 6355955 | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation | Mark I. Gardner, H. Jim Fulford | 2002-03-12 |
| 6300661 | Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate | Mark I. Gardner, Michael Duane | 2001-10-09 |
| 6261885 | Method for forming integrated circuit gate conductors from dual layers of polysilicon | Jon D. Cheek, Mark W. Michael | 2001-07-17 |
| 6259118 | Ultra high density NOR gate using a stacked transistor arrangement | Mark I. Gardner | 2001-07-10 |
| 6245649 | Method for forming a retrograde impurity profile | James F. Buller, Jon D. Cheek, Derick J. Wristers, H. Jim Fulford | 2001-06-12 |
| 6232637 | Semiconductor fabrication having multi-level transistors and high density interconnect therebetween | Mark I. Gardner | 2001-05-15 |
| 6225151 | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +2 more | 2001-05-01 |
| 6218251 | Asymmetrical IGFET devices with spacers formed by HDP techniques | Mark I. Gardner | 2001-04-17 |