Issued Patents All Time
Showing 26–50 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6172381 | Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall | Mark I. Gardner | 2001-01-09 |
| 6172402 | Integrated circuit having transistors that include insulative punchthrough regions and method of formation | Mark I. Gardner, Mark C. Gilmer | 2001-01-09 |
| 6150695 | Multilevel transistor formation employing a local substrate formed within a shallow trench | Mark I. Gardner, Derick J. Wristers | 2000-11-21 |
| 6140163 | Method and apparatus for upper level substrate isolation integrated with bulk silicon | Mark I. Gardner, Thomas E. Spikes, Jr. | 2000-10-31 |
| 6137145 | Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon | Jon D. Cheek, Mark W. Michael | 2000-10-24 |
| 6121643 | Semiconductor device having a group of high performance transistors and method of manufacture thereof | Mark I. Gardner | 2000-09-19 |
| 6111298 | Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length | Mark I. Gardner, Michael Duane | 2000-08-29 |
| 6104069 | Semiconductor device having an elevated active region formed in an oxide trench | Michael Duane, Mark I. Gardner | 2000-08-15 |
| 6104064 | Asymmetrical transistor structure | Mark I. Gardner, Michael Duane, Jon D. Cheek, Fred N. Hause, Robert Dawson +1 more | 2000-08-15 |
| 6097096 | Metal attachment method and structure for attaching substrates at low temperatures | Mark I. Gardner, Fred N. Hause | 2000-08-01 |
| 6096591 | Method of making an IGFET and a protected resistor with reduced processing steps | Mark I. Gardner, Derick J. Wristers | 2000-08-01 |
| 6083778 | Localized semiconductor substrate for multilevel for transistors | Mark I. Gardner | 2000-07-04 |
| 6080640 | Metal attachment method and structure for attaching substrates at low temperatures | Mark I. Gardner, Fred N. Hause | 2000-06-27 |
| 6078080 | Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region | Mark I. Gardner, Robert Dawson | 2000-06-20 |
| 6077748 | Advanced trench isolation fabrication scheme for precision polysilicon gate control | Mark I. Gardner, Michael Duane | 2000-06-20 |
| 6075268 | Ultra high density inverter using a stacked transistor arrangement | Mark I. Gardner | 2000-06-13 |
| 6075258 | Elevated transistor fabrication technique | Mark I. Gardner, Michael Duane | 2000-06-13 |
| 6069398 | Thin film resistor and fabrication method thereof | Mark I. Gardner, Frederick N. Hause | 2000-05-30 |
| 6069046 | Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment | Mark I. Gardner, Michael Duane | 2000-05-30 |
| 6051876 | Semiconductor device with a graded passivation layer | Mark I. Gardner, Sey-Ping Sun | 2000-04-18 |
| 6051459 | Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate | Mark I. Gardner, Frederick N. Hause, Derick J. Wristers | 2000-04-18 |
| 6048803 | Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines | Mark I. Gardner | 2000-04-11 |
| 6046471 | Ultra shallow junction depth transistors | Mark I. Gardner, Fred N. Hause | 2000-04-04 |
| 6040220 | Asymmetrical transistor formed from a gate conductor of unequal thickness | Mark I. Gardner, Michael Duane | 2000-03-21 |
| 6037629 | Trench transistor and isolation trench | Mark I. Gardner, Jon D. Cheek | 2000-03-14 |