Issued Patents All Time
Showing 51–75 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6030860 | Elevated substrate formation and local interconnect integrated fabrication | Mark I. Gardner, Michael Duane | 2000-02-29 |
| 6027964 | Method of making an IGFET with a selectively doped gate in combination with a protected resistor | Mark I. Gardner, Michael Duane | 2000-02-22 |
| 6027978 | Method of making an IGFET with a non-uniform lateral doping profile in the channel region | Mark I. Gardner, Michael Duane | 2000-02-22 |
| 6025633 | Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor | Mark I. Gardner | 2000-02-15 |
| 6010957 | Semiconductor device having tapered conductive lines and fabrication thereof | Mark I. Gardner | 2000-01-04 |
| 6008096 | Ultra short transistor fabrication method | Mark I. Gardner, Michael Duane | 1999-12-28 |
| 6005272 | Trench transistor with source contact in trench | Mark I. Gardner, Frederick N. Hause | 1999-12-21 |
| 6004849 | Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source | Mark I. Gardner, Michael Duane | 1999-12-21 |
| 5994779 | Semiconductor fabrication employing a spacer metallization technique | Mark I. Gardner, Fred N. Hause | 1999-11-30 |
| 5985724 | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer | Mark I. Gardner | 1999-11-16 |
| 5981354 | Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process | Thomas E. Spikes, Jr., Fred N. Hause | 1999-11-09 |
| 5970375 | Semiconductor fabrication employing a local interconnect | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-10-19 |
| 5970311 | Method and structure for optimizing the performance of a semiconductor device having dense transistors | Jon Cheek, Derick J. Wristers | 1999-10-19 |
| 5969394 | Method and structure for high aspect gate and short channel length insulated gate field effect transistors | Mark I. Gardner | 1999-10-19 |
| 5959337 | Air gap spacer formation for high performance MOSFETs | Mark I. Gardner, Michael Duane | 1999-09-28 |
| 5952696 | Complementary metal oxide semiconductor device with selective doping | Mark I. Gardner | 1999-09-14 |
| 5949092 | Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator | Mark I. Gardner, Michael Duane | 1999-09-07 |
| 5943562 | Semiconductor fabrication employing a transistor gate coupled to a localized substrate | Mark I. Gardner, Michael Duane | 1999-08-24 |
| 5937301 | Method of making a semiconductor device having sidewall spacers with improved profiles | Mark I. Gardner | 1999-08-10 |
| 5935766 | Method of forming a conductive plug in an interlevel dielectric | Jon D. Cheek, Derick J. Wristers | 1999-08-10 |
| 5933721 | Method for fabricating differential threshold voltage transistor pair | Frederick N. Hause, Mark I. Gardner | 1999-08-03 |
| 5930592 | Asymmetrical n-channel transistor having LDD implant only in the drain region | Brad Moore, Jon D. Cheek | 1999-07-27 |
| 5926700 | Semiconductor fabrication having multi-level transistors and high density interconnect therebetween | Mark I. Gardner | 1999-07-20 |
| 5923982 | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps | Mark I. Gardner, Robert Dawson | 1999-07-13 |
| 5912188 | Method of forming a contact hole in an interlevel dielectric layer using dual etch stops | Mark I. Gardner, Frederick N. Hause | 1999-06-15 |