Issued Patents All Time
Showing 76–100 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5909622 | Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant | Mark I. Gardner | 1999-06-01 |
| 5904529 | Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate | Mark I. Gardner | 1999-05-18 |
| 5898189 | Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method | Mark I. Gardner, Michael Duane | 1999-04-27 |
| 5893739 | Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer | Fred N. Hause, Jon D. Cheek | 1999-04-13 |
| 5888872 | Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall | Mark I. Gardner | 1999-03-30 |
| 5888853 | Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof | Mark I. Gardner, Michael Duane | 1999-03-30 |
| 5885877 | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +2 more | 1999-03-23 |
| 5885761 | Semiconductor device having an elevated active region formed from a thick polysilicon layer and method of manufacture thereof | Michael Duane, Mark I. Gardner | 1999-03-23 |
| 5882959 | Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor | Mark I. Gardner | 1999-03-16 |
| 5874341 | Method of forming trench transistor with source contact in trench | Mark I. Gardner, Frederick N. Hause | 1999-02-23 |
| 5872038 | Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof | Michael Duane, Mark I. Gardner | 1999-02-16 |
| 5872029 | Method for forming an ultra high density inverter using a stacked transistor arrangement | Mark I. Gardner | 1999-02-16 |
| 5869379 | Method of forming air gap spacer for high performance MOSFETS' | Mark I. Gardner, Michael Duane | 1999-02-09 |
| 5866934 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure | Mark I. Gardner, Jon D. Cheek | 1999-02-02 |
| 5863818 | Multilevel transistor fabrication method having an inverted, upper level transistor | Mark I. Garnder, Robert Paiz | 1999-01-26 |
| 5854115 | Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length | Mark I. Gardner, Michael Duane | 1998-12-29 |
| 5852310 | Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto | Mark I. Garnder, Jon D. Cheek | 1998-12-22 |
| 5851883 | High density integrated circuit process | Mark I. Gardner, Fred N. Hause | 1998-12-22 |
| 5849643 | Gate oxidation technique for deep sub quarter micron transistors | Mark C. Gilmer, Mark I. Gardner | 1998-12-15 |
| 5841168 | High performance asymmetrical MOSFET structure and method of making the same | Mark I. Gardner, Fred N. Hause | 1998-11-24 |
| 5834354 | Ultra high density NOR gate using a stacked transistor arrangement | Mark I. Gardner | 1998-11-10 |
| 5834350 | Elevated transistor fabrication technique | Mark I. Gardner, Michael Duane | 1998-11-10 |
| 5818069 | Ultra high density series-connected transistors formed on separate elevational levels | Mark I. Gardner | 1998-10-06 |
| 5808319 | Localized semiconductor substrate for multilevel transistors | Mark I. Gardner | 1998-09-15 |
| 5795807 | Semiconductor device having a group of high performance transistors and method of manufacture thereof | Mark I. Gardner | 1998-08-18 |