JB

John J. Bush

AM AMD: 10 patents #1,209 of 9,279Top 15%
VS Viavi Solutions: 10 patents #40 of 390Top 15%
FA Fasl: 1 patents #23 of 52Top 45%
TR Trilithic: 1 patents #13 of 16Top 85%
Overall (All Time): #157,306 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12225183 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2025-02-11
12206557 Intelligent monitoring and testing system for cable network Robert J. Flask, Raleigh Benton Stelle, IV, Alvin R. RUTH 2025-01-21
11856182 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2023-12-26
11509954 CATV return band sweeping using data over cable service interface specification carriers Gary W. Sinde 2022-11-22
11212517 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2021-12-28
10771777 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2020-09-08
10728539 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2020-07-28
10623809 CATV return band sweeping using data over cable service interface specification carrier Gary W. Sinde 2020-04-14
10116930 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2018-10-30
10110888 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2018-10-23
9667956 Icon-based home certification, in-home leakage testing, and antenna matching pad Terry W. Bush, Dexin Sun 2017-05-30
9654218 RF ingress in fiber-to-the-premises Terry W. Bush, Gary W. Sinde 2017-05-16
6977195 Test structure for characterizing junction leakage current Wen-Jie Qi, Robert H. Dawson 2005-12-20
6469316 Test structure to monitor the effects of polysilicon pre-doping Mark I. Gardner, David E. Brown 2002-10-22
6429052 Method of making high performance transistor with a reduced width gate electrode and device comprising same Mark I. Gardner, Frederick N. Hause 2002-08-06
6380554 Test structure for electrically measuring the degree of misalignment between successive layers of conductors H. Jim Fulford, Mark I. Gardner 2002-04-30
6359461 Test structure for determining the properties of densely packed transistors Jon D. Cheek, H. Jim Fulford 2002-03-19
6191446 Formation and control of a vertically oriented transistor channel length Mark I. Gardner, Jon D. Cheek 2001-02-20
6130454 Gate conductor formed within a trench bounded by slanted sidewalls Mark I. Gardner, Jon D. Cheek 2000-10-10
6110786 Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof Mark I. Gardner, Jon D. Cheek 2000-08-29
6075417 Ring oscillator test structure Jon D. Cheek, Antonio Torres Garcia 2000-06-13
5986283 Test structure for determining how lithographic patterning of a gate conductor affects transistor properties Jon D. Cheek, Mark I. Gardner 1999-11-16
5918128 Reduced channel length for a high performance CMOS transistor Mark I. Gardner 1999-06-29
D400038 Shelf Richard J. Herman 1998-10-27
D390728 Display shelf Richard J. Herman 1998-02-17