Issued Patents All Time
Showing 26–50 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6261908 | Buried local interconnect | Mark I. Gardner, Charles E. May | 2001-07-17 |
| 6259142 | Multiple split gate semiconductor device and fabrication method | Robert Dawson, Mark I. Gardner, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2001-07-10 |
| 6255703 | Device with lower LDD resistance | Manfred Horstmann, Karsten Wieczorek | 2001-07-03 |
| 6255182 | Method of forming a gate structure of a transistor by means of scalable spacer technology | Karsten Wieczorek, Manfred Horstmann | 2001-07-03 |
| 6252283 | CMOS transistor design for shared N+/P+ electrode with enhanced device performance | Mark I. Gardner, Dim-Lee Kwong | 2001-06-26 |
| 6242776 | Device improvement by lowering LDD resistance with new silicide process | Manfred Horstmann, Karsten Wieczorek | 2001-06-05 |
| 6226781 | Modifying a design layer of an integrated circuit using overlying and underlying design layers | John L. Nistler, Phillip J. Etter | 2001-05-01 |
| 6225151 | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Daniel Kadosh, Mark W. Michael +2 more | 2001-05-01 |
| 6218250 | Method and apparatus for minimizing parasitic resistance of semiconductor devices | Karsten Wieczorek, Manfred Horstmann | 2001-04-17 |
| 6207563 | Low-leakage CoSi2-processing by high temperature thermal processing | Karsten Wieczorek, Manfred Horstmann | 2001-03-27 |
| 6201278 | Trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2001-03-13 |
| 6200862 | Mask for asymmetrical transistor formation with paired transistors | Mark I. Gardner, Michael Duane | 2001-03-13 |
| 6197645 | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls | Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Bradley T. Moore +1 more | 2001-03-06 |
| 6194768 | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure | Mark I. Gardner, Charles E. May | 2001-02-27 |
| 6188107 | High performance transistor fabricated on a dielectric film and method of making same | Mark I. Gardner, Derick J. Wristers | 2001-02-13 |
| 6188114 | Method of forming an insulated-gate field-effect transistor with metal spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2001-02-13 |
| 6166354 | System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more | 2000-12-26 |
| 6163059 | Integrated circuit including source implant self-aligned to contact via | Mark I. Gardner | 2000-12-19 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Bradley T. Moore +1 more | 2000-11-14 |
| 6146983 | Method of making semiconductor device having sacrificial salicidation layer | Mark I. Gardner, Charles E. May | 2000-11-14 |
| 6140167 | High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation | Mark I. Gardner, Mark C. Gilmer | 2000-10-31 |
| 6140674 | Buried trench capacitor | Mark I. Gardner, Charles E. May | 2000-10-31 |
| 6140677 | Semiconductor topography for a high speed MOSFET having an ultra narrow gate | Mark I. Gardner | 2000-10-31 |
| 6133124 | Device improvement by source to drain resistance lowering through undersilicidation | Manfred Horstmann, Karsten Wieczorek | 2000-10-17 |
| 6127234 | Ultra shallow extension formation using disposable spacers | Mark I. Gardner, Charles E. May | 2000-10-03 |