MB

Mark A. Brittain

IBM: 25 patents #4,217 of 70,183Top 7%
NV NVIDIA: 1 patents #4,316 of 7,811Top 60%
Overall (All Time): #154,980 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 25 most recent of 26 patents

Patent #TitleCo-InventorsDate
9785578 Apparatus and method for controlling access to a memory device Michael Andrew Campbell 2017-10-10
9632954 Memory queue handling techniques for reducing impact of high-latency memory operations John Steven Dodson, Benjiman L. Goodman, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli 2017-04-25
8996824 Memory reorder queue biasing preceding high latency operations John Steven Dodson, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli 2015-03-31
8909874 Memory reorder queue biasing preceding high latency operations John Steven Dodson, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli 2014-12-09
8543759 Method for scheduling memory refresh operations including power states John Steven Dodson, Benjamin Lee Goodman, Stephen J. Powell, Jeffrey A. Stuecheli 2013-09-24
8539146 Apparatus for scheduling memory refresh operations including power states John Steven Dodson, Benjiman L. Goodman, Stephen J. Powell, Jeffrey A. Stuecheli 2013-09-17
8055922 Power management via DIMM read operation limiter Warren E. Maule 2011-11-08
7934070 Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices Edgar R. Cordero, Sanjeev Ghai, Warren E. Maule 2011-04-26
7930469 System to provide memory system power reduction without reducing overall memory system performance Kevin C. Gower, Warren E. Maule 2011-04-19
7930470 System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller Kevin C. Gower, Warren E. Maule 2011-04-19
7925825 System to support a full asynchronous interface within a memory hub device Kevin C. Gower, Warren E. Maule 2011-04-12
7925826 System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency Kevin C. Gower, Warren E. Maule 2011-04-12
7925824 System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency Kevin C. Gower, Warren E. Maule 2011-04-12
7840860 Double DRAM bit steering for multiple error corrections Luiz C. Alves, Timothy J. Dell, Sanjeev Ghai, Warren E. Maule, Scott Barnett Swaney 2010-11-23
7631228 Using bit errors from memory to alter memory command stream Warren E. Maule 2009-12-08
7600091 Executing background writes to idle DIMMS Warren E. Maule, Gary Alan Morrison, Jeffrey A. Stuecheli 2009-10-06
7587559 Systems and methods for memory module power management Warren E. Maule, Karthick Rajamani, Eric E. Retter, Robert B. Tremaine 2009-09-08
7571357 Memory wrap test mode using functional read/write buffers Edgar R. Cordero, John T. Hollaway, Jr., Eric E. Retter 2009-08-04
7523364 Double DRAM bit steering for multiple error corrections Luiz C. Alves, Timothy J. Dell, Sanjeev Ghai, Warren E. Maule, Scott Barnett Swaney 2009-04-21
7516264 Programmable bank/timer address folding in memory devices Warren E. Maule, Gary Alan Morrison, Jeffrey A. Stuecheli 2009-04-07
7493456 Memory queue with supplemental locations for consecutive addresses Warren E. Maule, Eric E. Retter 2009-02-17
7426649 Power management via DIMM read operation limiter Warren E. Maule 2008-09-16
7421598 Dynamic power management via DIMM read operation limiter Edgar R. Cordero, James Stephen Fields, Jr., Warren E. Maule, Eric E. Retter 2008-09-02
7373471 Executing background writes to idle DIMMs Warren E. Maule, Gary Alan Morrison, Jeffrey A. Stuecheli 2008-05-13
7337293 Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices Edgar R. Cordero, Sanjeev Ghai, Warren E. Maule 2008-02-26