Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11947462 | Cache footprint management | Yoong Chert Foo, Terence M. Potter, Benjiman L. Goodman, Aroun Demeure, Cheng Li +1 more | 2024-04-02 |
| 9317427 | Reallocating unused memory databus utilization to another processor when utilization is below a threshold | Rajendra D. Panda, Venkat R. Indukuru, Joseph H. Robichaux, Robert H. Bell, Jr., Steven Paul Hartman | 2016-04-19 |
| 9135142 | Workload performance projection for future information handling systems using microarchitecture dependent data | Robert H. Bell, Jr., Luigi Brochard, Venkat R. Indukuru, Rajendra D. Panda, Sameh S. Sharkawi | 2015-09-15 |
| 9098351 | Energy-aware job scheduling for cluster environments | Robert H. Bell, Jr., Luigi Brochard, Rajendra D. Panda, Francois Thomas | 2015-08-04 |
| 8898674 | Memory databus utilization management system and computer program product | Rajendra D. Panda, Venkat R. Indukuru, Joseph H. Robichaux, Robert H. Bell, Jr., Steven Paul Hartman | 2014-11-25 |
| 8612984 | Energy-aware job scheduling for cluster environments | Robert H. Bell, Jr., Luigi Brochard, Rajendra D. Panda, Francois Thomas | 2013-12-17 |
| 8589656 | Queuing of conflicted remotely received transactions | Robert Joersz, Davis A. Miller, Maged M. Michael | 2013-11-19 |
| 8578130 | Partitioning of node into more than one partition | Bruce M. Gilbert, Robert Joersz, Wayne A. Downer | 2013-11-05 |
| 8527997 | Energy-aware job scheduling for cluster environments | Robert H. Bell, Jr., Luigi Brochard, Rajendra D. Panda, Francois Thomas | 2013-09-03 |
| 8527956 | Workload performance projection via surrogate program analysis for future information handling systems | Robert H. Bell, Jr., Luigi Brochard, Venkat R. Indukuru, Rajendra D. Panda, Sameh S. Sharkawi | 2013-09-03 |
| 8347124 | Workload power consumption projection on information handling system | Robert H. Bell, Jr., Rajendra D. Panda, Joseph H. Robichaux, Venkat R. Indukuru, Sameh S. Sharkawi | 2013-01-01 |
| 8250330 | Memory controller having tables mapping memory addresses to memory modules | Eric N. Lais, Michael Grassi, Bruce M. Gilbert | 2012-08-21 |
| 8229867 | Bit-selection for string-based genetic algorithms | Jason F. Cantin | 2012-07-24 |
| 8015248 | Queuing of conflicted remotely received transactions | Robert Joersz, Davis A. Miller, Maged M. Michael | 2011-09-06 |
| 7861126 | Implementation-efficient multiple-counter value hardware performance counter | Carl E. Love, Jaeheon Jeong, Russell M. Clapp | 2010-12-28 |
| 7827449 | Non-inline transaction error correction | Bruce M. Gilbert, Robert Joersz | 2010-11-02 |
| 7669010 | Prefetch miss indicator for cache coherence directory misses on external caches | Eric N. Lais, Rob Joersz | 2010-02-23 |
| 7594080 | Temporary storage of memory line while waiting for cache eviction | Thomas D. Lovett, Maged M. Michael, Robert Joersz | 2009-09-22 |
| 7529800 | Queuing of conflicted remotely received transactions | Robert Joersz, Davis A. Miller, Maged M. Michael | 2009-05-05 |
| 7437622 | Implementation-efficient multiple-counter value hardware performance counter | Carl E. Love, Jaeheon Jeong, Russell M. Clapp | 2008-10-14 |
| 7395375 | Prefetch miss indicator for cache coherence directory misses on external caches | Eric N. Lais, Rob Joersz | 2008-07-01 |
| 7383464 | Non-inline transaction error correction | Bruce M. Gilbert, Robert Joersz | 2008-06-03 |
| 7337352 | Cache entry error-connecting code (ECC) based at least on cache entry data and memory address | — | 2008-02-26 |
| 7272754 | Implementation-efficient multiple-counter value hardware performance counter | Carl E. Love, Jaeheon Jeong, Russell M. Clapp | 2007-09-18 |
| 7210018 | Multiple-stage pipeline for transaction conversion | Bruce M. Gilbert, Robert Joersz, Thomas D. Lovett, Maged M. Michael | 2007-04-24 |