Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10255450 | Customer load of field programmable gate arrays | Todd W. Arnold, Vincenzo Condorelli | 2019-04-09 |
| 10108569 | Arbitration in an SRIOV environment | Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez | 2018-10-23 |
| 10102165 | Arbitration in an SRIOV environment | Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez | 2018-10-16 |
| 9875367 | Customer load of field programmable gate arrays | Todd W. Arnold, Vincenzo Condorelli | 2018-01-23 |
| 9703973 | Customer load of field programmable gate arrays | Todd W. Arnold, Vincenzo Condorelli | 2017-07-11 |
| 8656228 | Memory error isolation and recovery in a multiprocessor computer system | David F. Craddock, Thomas A. Gregg, Pak-kin Mak, Gary E. Strait | 2014-02-18 |
| 8555234 | Verification of soft error resilience | Robert B. Tremaine, Pia Naoko Sanda, Prabhakar Kudva | 2013-10-08 |
| 8438415 | Performing a perform timing facility function instruction for synchronizing TOD clocks | Eberhard Engler, Mark S. Farrell, Klaus Meissner, Ronald M. Smith, Sr. | 2013-05-07 |
| 8433950 | System to determine fault tolerance in an integrated circuit and associated methods | Andrew R. Ranck, Robert B. Tremaine | 2013-04-30 |
| 8135978 | Performing a perform timing facility function instruction for sychronizing TOD clocks | Eberhard Engler, Mark S. Farrell, Klaus Meissner, Ronald M. Smith, Sr. | 2012-03-13 |
| 8090883 | Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance | Gary E. Strait, Hong Deng, Diana L. Orf, Hanno Ulrich | 2012-01-03 |
| 7886089 | Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance | Gary E. Strait, Hong Deng, Diana L. Orf | 2011-02-08 |
| 7882278 | Utilizing programmable channels for allocation of buffer space and transaction control in data communications | Sundeep Chadha, Bernard C. Drerup, Michael Grassi | 2011-02-01 |
| 7739545 | System and method to support use of bus spare wires in connection modules | Jonathan Y. Chen, Thomas G. Foote, Timothy J. Slegel | 2010-06-15 |
| 7725894 | Enhanced un-privileged computer instruction to store a facility list | John R. Ehrman, Mark S. Farrell, Mike S. Fulton, Charles W. Gainey, Jr., Dan F. Greiner +2 more | 2010-05-25 |
| 7647435 | Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism | Bernard C. Drerup, Michael Grassi | 2010-01-12 |
| 7617410 | Simultaneously updating logical time of day (TOD) clocks for multiple cpus in response to detecting a carry at a pre-determined bit position of a physical clock | Ronald M. Smith, Sr. | 2009-11-10 |
| 7493426 | Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control | Sundeep Chadha, Bernard C. Drerup, Michael Grassi | 2009-02-17 |
| 7277974 | Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism | Bernard C. Drerup, Michael Grassi | 2007-10-02 |
| 7249207 | Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domains | Bernard C. Drerup, Michael Grassi | 2007-07-24 |
| 7167968 | Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data | Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, John G. Rell, Jr., Frank Tanzi | 2007-01-23 |
| 7136954 | Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism | Bernard C. Drerup, Michael Grassi | 2006-11-14 |
| 7103754 | Computer instructions for having extended signed displacement fields for finding instruction operands | Brian B. Moore, Timothy J. Slegel | 2006-09-05 |
| 7089408 | Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution | Jennifer A. Navarro, Chung-Lung K. Shum | 2006-08-08 |
| 7035986 | System and method for simultaneous access of the same line in cache storage | Jennifer A. Navarro, Chung-Lung K. Shum, Timothy J. Slegel, Aaron Tsai | 2006-04-25 |