Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6990556 | System and method for simultaneous access of the same doubleword in cache storage | Aaron Tsai | 2006-01-24 |
| 6973552 | System and method to handle page validation with out-of-order fetch | — | 2005-12-06 |
| 6865645 | Program store compare handling between instruction and operand caches | Chung-Lung K. Shum, Dean G. Bair, Charles F. Webb, John S. Liptay | 2005-03-08 |
| 6751708 | Method for ensuring that a line is present in an instruction cache | John S. Liptay, Mark S. Farrell, Bruce C. Giamei, Charles F. Webb | 2004-06-15 |
| 6745313 | Absolute address bits kept in branch history table | John S. Liptay, Brian R. Prasky, Chung-Lung K. Shum | 2004-06-01 |
| 6671794 | Address generation interlock detection | Bruce C. Giamei, John S. Liptay | 2003-12-30 |
| 6178495 | Processor E-unit to I-unit interface instruction modification with E-unit opcode computer logic in the unit | Timothy J. Slegel | 2001-01-23 |
| 6138223 | Absolute address history table index generation for predicting instruction and operand cache accesses | John S. Liptay | 2000-10-24 |
| 6138215 | Method for absolute address history table synonym resolution | Jane H. Bartik | 2000-10-24 |
| 6125444 | Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all | John S. Liptay, Timothy J. Slegel, Charles F. Webb, Mark S. Farrell | 2000-09-26 |
| 6108776 | Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer | John S. Liptay, Timothy J. Slegel, Charles F. Webb, Mark S. Farrell | 2000-08-22 |
| 6105126 | Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code | Ronald M. Smith, Sr., John S. Liptay, Eric M. Schwarz, Timothy J. Slegel, Charles F. Webb | 2000-08-15 |
| 6092185 | Opcode compare logic in E-unit for breaking infinite loops, detecting invalid opcodes and other exception checking | Timothy J. Slegel | 2000-07-18 |
| 6085313 | Computer processor system for executing RXE format floating point instructions | Ronald M. Smith, Sr., John S. Liptay, Eric M. Schwarz, Timothy J. Slegel, Charles F. Webb | 2000-07-04 |
| 6035392 | Computer with optimizing hardware for conditional hedge fetching into cache storage | John S. Liptay, Barry W. Krumm, Jennifer A. Navarro, Charles F. Webb | 2000-03-07 |
| 6026488 | Method for conditional hedge fetching into cache storage | John S. Liptay, Barry W. Krumm, Jennifer A. Navarro, Charles F. Webb | 2000-02-15 |
| 5903479 | Method and system for executing denormalized numbers | Eric M. Schwarz, Bruce C. Giamei, Christopher A. Krygowski, John S. Liptay | 1999-05-11 |
| 5790844 | Millicode load and test access instruction that blocks interrupts in response to access exceptions | Charles F. Webb, Mark S. Farrell, John S. Liptay | 1998-08-04 |
| 5748951 | Specialized millicode instructions which reduce cycle time and number of instructions necessary to perform complex operations | Charles F. Webb, Mark S. Farrell, John S. Liptay | 1998-05-05 |
| 5694587 | Specialized millicode instructions for test PSW validity, load with access test, and character translation assist | Charles F. Webb, Mark S. Farrell, John S. Liptay | 1997-12-02 |
| 5625808 | Read only store as part of cache store for storing frequently used millicode instructions | Charles F. Webb, Mark S. Farrell, Barry W. Krumm, John S. Liptay, Jennifer Serena Almoradie Navarro +1 more | 1997-04-29 |