Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11748238 | Model-based biased random system test through rest API | Vitali Sokhin, Gil Eliezer Shurek, Shiri Moran, Tom Kolan | 2023-09-05 |
| 10678670 | Evaluating fairness in devices under test | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis | 2020-06-09 |
| 10671506 | Evaluating fairness in devices under test | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis | 2020-06-02 |
| 10289512 | Persistent command parameter table for pre-silicon device testing | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam | 2019-05-14 |
| 10061679 | Evaluating fairness in devices under test | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis | 2018-08-28 |
| 10055327 | Evaluating fairness in devices under test | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis | 2018-08-21 |
| 9990290 | Cache coherency verification using ordered lists | Jonathan T. Hsieh, Matthew G. Pardini, Eugene S. Rotter | 2018-06-05 |
| 9892010 | Persistent command parameter table for pre-silicon device testing | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam | 2018-02-13 |
| 9665280 | Cache coherency verification using ordered lists | Jonathan T. Hsieh, Matthew G. Pardini, Eugene S. Rotter | 2017-05-30 |
| 9665281 | Cache coherency verification using ordered lists | Jonathan T. Hsieh, Matthew G. Pardini, Eugene S. Rotter | 2017-05-30 |
| 9619312 | Persistent command parameter table for pre-silicon device testing | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam | 2017-04-11 |
| 9524801 | Persistent command parameter table for pre-silicon device testing | Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam | 2016-12-20 |
| 8271932 | Hierarchical error injection for complex RAIM/ECC design | Patrick J. Meaney, Luis A. Lastras-Montano, Alia Shah, Eldee Stephens | 2012-09-18 |
| 7996203 | Method, system, and computer program product for out of order instruction address stride prefetch performance verification | Wei-Yi Xiao, Christopher A. Krygowski, Chung-Lung K. Shum | 2011-08-09 |
| 7559002 | Multi-thread parallel segment scan simulation of chip element performance | Wei-Yi Xiao, Thomas Ruane, William J. Lewis | 2009-07-07 |
| 7213122 | Controlling the generation and selection of addresses to be used in a verification environment | Edward J. Kaminski, Jr., James Lyle Schafer | 2007-05-01 |
| 7089518 | Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks | Edward J. Kaminski, Jr., Bradley Nelson | 2006-08-08 |
| 6865645 | Program store compare handling between instruction and operand caches | Chung-Lung K. Shum, Charles F. Webb, Mark A. Check, John S. Liptay | 2005-03-08 |
| 6560687 | Method of implementing a translation lookaside buffer with support for a real space control | Aaron Tsai, Chung-Lung K. Shum, Rebecca S. Wisniewski, Charles F. Webb | 2003-05-06 |
| 6119219 | System serialization with early release of individual processor | Charles F. Webb, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak, Jennifer A. Navarro +1 more | 2000-09-12 |
| 6079013 | Multiprocessor serialization with early release of processors | Charles F. Webb, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak, Jennifer A. Navarro +1 more | 2000-06-20 |
| 5745386 | Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram | Bruce Wile, Edward J. Kaminski, Jr. | 1998-04-28 |