JH

Jonathan T. Hsieh

IBM: 39 patents #2,420 of 70,183Top 4%
Overall (All Time): #82,166 of 4,157,543Top 2%
39
Patents All Time

Issued Patents All Time

Showing 25 most recent of 39 patents

Patent #TitleCo-InventorsDate
12099845 Load reissuing using an alternate issue queue Gregory W. Alexander, Aaron Tsai, Yossi Shapira 2024-09-24
11243774 Dynamic selection of OSC hazard avoidance mechanism James R. Cuffney, Adam B. Collura, James J. Bonanno, Edward T. Malley, Anthony Saporito +2 more 2022-02-08
11205005 Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data Matthew Michael Garcia Pardini, Gregory W. Alexander, Michael P. Mullen, Olaf K. Hendrickson 2021-12-21
11150902 Processor pipeline management during cache misses using next-best ticket identifier for sleep and wakeup Taylor J. Pritchard, Michael J. Cadigan, Jr. 2021-10-19
11144367 Write power optimization for hardware employing pipe-based duplicate register files Richard Joseph Branciforte, Gregory W. Alexander, Avraham Ayzenfeld, Edward T. Malley, Gregory Miaskovsky 2021-10-12
11144321 Store hit multiple load side register for preventing a subsequent store memory violation Yair Fried, Eyal Naor, James J. Bonanno, Gregory W. Alexander 2021-10-12
11080199 Determining logical address of an oldest memory access request Yossi Shapira, Michael J. Cadigan, Jr., Jane H. Bartik, Taylor J. Pritchard 2021-08-03
11074184 Maintaining data order between buffers Michael J. Cadigan, Jr., Erez Barak, Deepankar Bhattacharjee, Yair Fried, Martin Recktenwald +1 more 2021-07-27
10963259 Accounting for multiple pipeline depths in processor instrumentation Avery Francois, Gregory W. Alexander 2021-03-30
10929142 Making precise operand-store-compare predictions to avoid false dependencies Gregory W. Alexander, James J. Bonanno, Adam B. Collura, James R. Cuffney, Yair Fried +4 more 2021-02-23
10802830 Imprecise register dependency tracking Gregory W. Alexander, Tu-An T. Nguyen 2020-10-13
10296348 Delayed allocation of an out-of-order queue entry and based on determining that the entry is unavailable, enable deadlock avoidance involving reserving one or more entries in the queue, and disabling deadlock avoidance based on expiration of a predetermined amount of time Khary J. Alexander, Ilya Granovsky, Christian Jacobi 2019-05-21
9990290 Cache coherency verification using ordered lists Dean G. Bair, Matthew G. Pardini, Eugene S. Rotter 2018-06-05
9940264 Load and store ordering for a strongly ordered simultaneous multithreading core Khary J. Alexander, Christian Jacobi, Martin Recktenwald 2018-04-10
9886397 Load and store ordering for a strongly ordered simultaneous multithreading core Khary J. Alexander, Christian Jacobi, Martin Recktenwald 2018-02-06
9697132 Store forwarding cache Khary J. Alexander, Christian Jacobi, James R. Mitchell 2017-07-04
9665280 Cache coherency verification using ordered lists Dean G. Bair, Matthew G. Pardini, Eugene S. Rotter 2017-05-30
9665281 Cache coherency verification using ordered lists Dean G. Bair, Matthew G. Pardini, Eugene S. Rotter 2017-05-30
9612963 Store forwarding cache Khary J. Alexander, Christian Jacobi, James R. Mitchell 2017-04-04
9569370 Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB) Khary J. Alexander, Christian Jacobi, Timothy J. Slegel 2017-02-14
9483409 Store forwarding cache Khary J. Alexander, Christian Jacobi, James R. Mitchell 2016-11-01
9471504 Store forwarding cache Khary J. Alexander, Christian Jacobi, James R. Mitchell 2016-10-18
9460023 Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB) Khary J. Alexander, Christian Jacobi, Timothy J. Slegel 2016-10-04
9430235 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors Gregory W. Alexander, Khary J. Alexander, Brian W. Curran, Christian Jacobi, James R. Mitchell +2 more 2016-08-30
9400752 Store forwarding cache Khary J. Alexander, Christian Jacobi, James R. Mitchell 2016-07-26