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Using a shadow copy of a cache in a cache hierarchy |
Aaron Tsai, Eyal Naor, Christian Jacobi, Timothy C. Bronson, Chung-Lung K. Shum |
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| 11474821 |
Processor dependency-aware instruction execution |
Amir Turi, Avraham Ayzenfeld, Gilad Merran, Yanai Danan, Amit Shay +3 more |
2022-10-18 |
| 11157281 |
Prefetching data based on register-activity patterns |
Eyal Naor, Yossi Shapira, Amir Turi |
2021-10-26 |
| 11144321 |
Store hit multiple load side register for preventing a subsequent store memory violation |
Jonathan T. Hsieh, Eyal Naor, James J. Bonanno, Gregory W. Alexander |
2021-10-12 |
| 11074184 |
Maintaining data order between buffers |
Michael J. Cadigan, Jr., Erez Barak, Deepankar Bhattacharjee, Jonathan T. Hsieh, Martin Recktenwald +1 more |
2021-07-27 |
| 11029950 |
Reducing latency of common source data movement instructions |
Yossi Shapira, Eyal Naor, Amir Turi |
2021-06-08 |
| 10977040 |
Heuristic invalidation of non-useful entries in an array |
James R. Cuffney, Adam B. Collura, James J. Bonanno, Jang-Soo Lee, Eyal Naor +1 more |
2021-04-13 |
| 10929142 |
Making precise operand-store-compare predictions to avoid false dependencies |
Gregory W. Alexander, James J. Bonanno, Adam B. Collura, James R. Cuffney, Jonathan T. Hsieh +4 more |
2021-02-23 |
| 10649777 |
Hardware-based data prefetching based on loop-unrolled instructions |
Yossi Shapira, Eyal Naor, Gregory Miaskovsky |
2020-05-12 |
| 10572387 |
Hardware control of CPU hold of a cache line in private cache where cache invalidate bit is reset upon expiration of timer |
Dwifuzi Coe, Martin Recktenwald, Yossi Shapira |
2020-02-25 |
| 10382484 |
Detecting attackers who target containerized clusters |
Hanoch Shayevitz, Matan Kubovsky |
2019-08-13 |
