| 11443044 |
Targeted very long delay for increasing speculative execution progression |
Michael P. Mullen, Matthew Michael Garcia Pardini |
2022-09-13 |
| 11205005 |
Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data |
Matthew Michael Garcia Pardini, Gregory W. Alexander, Jonathan T. Hsieh, Michael P. Mullen |
2021-12-21 |
| 11106602 |
Memory blockade for verifying system security with respect to speculative execution |
Matthew Michael Garcia Pardini, Michael P. Mullen |
2021-08-31 |
| 10061672 |
Implementing random content of program loops in random test generation for processor verification |
Adi Dagan, Avishai Moshe Fedida, Oz Dov Hershkovitz |
2018-08-28 |
| 9734033 |
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads |
Yugi Morimoto, Michael P. Mullen, Michal Rimon |
2017-08-15 |
| 9720793 |
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads |
Yugi Morimoto, Michael P. Mullen, Michal Rimon |
2017-08-01 |
| 9251023 |
Implementing automated memory address recording in constrained random test generation for verification of processor hardware designs |
Craig Atherton, Avishai Moshe Fedida, Oz Dov Hershkovitz |
2016-02-02 |
| 8918678 |
Functional testing of a processor design |
Eli Almog, Christopher A. Krygowski |
2014-12-23 |
| 8275598 |
Software table walk during test verification of a simulated densely threaded network on a chip |
Anatoli Andreev, John Martin Ludden, Richard D. Peterson, Elena Tsanko |
2012-09-25 |
