Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10678670 | Evaluating fairness in devices under test | Dean G. Bair, Rebecca M. Gott, William J. Lewis | 2020-06-09 |
| 10671506 | Evaluating fairness in devices under test | Dean G. Bair, Rebecca M. Gott, William J. Lewis | 2020-06-02 |
| 10289512 | Persistent command parameter table for pre-silicon device testing | Dean G. Bair, Rebecca M. Gott, William J. Lewis, Chakrapani Rayadurgam | 2019-05-14 |
| 10061679 | Evaluating fairness in devices under test | Dean G. Bair, Rebecca M. Gott, William J. Lewis | 2018-08-28 |
| 10055327 | Evaluating fairness in devices under test | Dean G. Bair, Rebecca M. Gott, William J. Lewis | 2018-08-21 |
| 9892010 | Persistent command parameter table for pre-silicon device testing | Dean G. Bair, Rebecca M. Gott, William J. Lewis, Chakrapani Rayadurgam | 2018-02-13 |
| 9619312 | Persistent command parameter table for pre-silicon device testing | Dean G. Bair, Rebecca M. Gott, William J. Lewis, Chakrapani Rayadurgam | 2017-04-11 |
| 9524801 | Persistent command parameter table for pre-silicon device testing | Dean G. Bair, Rebecca M. Gott, William J. Lewis, Chakrapani Rayadurgam | 2016-12-20 |
| 9501283 | Cross-pipe serialization for multi-pipeline processor | Deanna Postles Dunn Berger, Michael Fee, Diane L. Orf | 2016-11-22 |
| 9378023 | Cross-pipe serialization for multi-pipeline processor | Deanna Postles Dunn Berger, Michael Fee, Diane L. Orf | 2016-06-28 |
| 8364904 | Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer | Michael A. Blake, Lawrence D. Curley, Garrett M. Drapala, Craig R. Walters | 2013-01-29 |
| 7483825 | Method for the creation of a hybrid cycle simulation model | Gary A. Van Huben, Elspeth Anne Huston | 2009-01-27 |
| 7213122 | Controlling the generation and selection of addresses to be used in a verification environment | Dean G. Bair, James Lyle Schafer | 2007-05-01 |
| 7089518 | Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks | Dean G. Bair, Bradley Nelson | 2006-08-08 |
| 5745386 | Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram | Bruce Wile, Dean G. Bair | 1998-04-28 |