Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10380031 | Ensuring forward progress for nested translations in a memory management unit | Guy L. Guthrie, Jody B. Joyner, Jon K. Kriegel, Charles D. Wait | 2019-08-13 |
| 10318435 | Ensuring forward progress for nested translations in a memory management unit | Guy L. Guthrie, Jody B. Joyner, Jon K. Kriegel, Charles D. Wait | 2019-06-11 |
| 8984261 | Store data forwarding with no memory model restrictions | Brian D. Barrick, Barry W. Krumm, James R. Mitchell, Aaron Tsai, Chung-Lung K. Shum +1 more | 2015-03-17 |
| 8627047 | Store data forwarding with no memory model restrictions | Aaron Tsai, Barry W. Krumm, James R. Mitchell, Brian D. Barrick, Chung-Lung K. Shum +1 more | 2014-01-07 |
| 8468306 | Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions | Aaron Tsai, Barry W. Krumm, James R. Mitchell, Brian D. Barrick, Chung-Lung K. Shum +1 more | 2013-06-18 |
| 8238190 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Yee Ja, Wolfgang Roesner | 2012-08-07 |
| 7995619 | Methods and arrangements to model an asynchronous interface | Yee Ja | 2011-08-09 |
| 7885801 | Modeling asynchronous behavior from primary inputs and latches | Zoltan T. Hidvegi, Yee Ja | 2011-02-08 |
| 7877717 | Accurately modeling an asynchronous interface using expanded logic elements | Bing-Lun Chu, Yee Ja, Wolfgang Roesner | 2011-01-25 |
| 7870528 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation | Yee Ja | 2011-01-11 |
| 7536288 | Method, system and program product supporting user tracing in a simulator | Wolfgang Roesner, Derek E. Williams | 2009-05-19 |
| 7519524 | Program product for providing a configuration specification language supporting incompletely specified configuration entities | Wolfgang Roesner, Derek E. Williams | 2009-04-14 |
| 7484196 | Method for asynchronous clock modeling in an integrated circuit simulation | Yee Ja | 2009-01-27 |
| 7484192 | Method for modeling metastability decay through latches in an integrated circuit model | Yee Ja | 2009-01-27 |
| 7453759 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Yee Ja, Wolfgang Roesner | 2008-11-18 |
| 7447620 | Modeling asynchronous behavior from primary inputs and latches | Zoltan T. Hidvegi, Yee Ja | 2008-11-04 |
| 7448015 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation | Yee Ja | 2008-11-04 |
| 7426461 | Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities | Wolfgang Roesner, Derek E. Williams | 2008-09-16 |
| 7302659 | System and method for unfolding/replicating logic paths to facilitate propagation delay modeling | Yee Ja | 2007-11-27 |
| 7299436 | System and method for accurately modeling an asynchronous interface using expanded logic elements | Bing-Lun Chu, Yee Ja, Wolfgang Roesner | 2007-11-20 |
| 7089518 | Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks | Dean G. Bair, Edward J. Kaminski, Jr. | 2006-08-08 |
| 6993729 | Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model | Wolfgang Roesner, Hugh Shen, Derek E. Williams | 2006-01-31 |