Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11588692 | System and method for providing an intelligent ephemeral distributed service model for server group provisioning | Cyril Jose, Marshal F. Savage, Chandrasekhar Puthillathe, Choudary Maddukuri | 2023-02-21 |
| 11196733 | System and method for group of groups single sign-on demarcation based on first user login | Marshal F. Savage, Cyril Jose, Srihari Srirangam, Anto DolphinJose Jesurajan Marystella, Farhan Syed | 2021-12-07 |
| 11153165 | System and method for providing an intelligent ephemeral distributed service model for server group provisioning | Cyril Jose, Marshal F. Savage, Chandrasekhar Puthillathe, Choudary Maddukuri | 2021-10-19 |
| 10855463 | System and method for providing quality of service during transport key rotation at a distributed management controller group | Marshal F. Savage, Cyril Jose | 2020-12-01 |
| 10798074 | System and method for preventing well behaving clients from causing account lockouts in a group | Marshal F. Savage, Cyril Jose | 2020-10-06 |
| 10594671 | System and method for preventing well behaving clients from causing account lockouts in a group | Marshal F. Savage, Cyril Jose | 2020-03-17 |
| 10230787 | System and method for managing distributed cluster identity | Thi D. Hyunh, Marshal F. Savage, Cyril Jose | 2019-03-12 |
| 8238190 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Bradley Nelson, Wolfgang Roesner | 2012-08-07 |
| 7995619 | Methods and arrangements to model an asynchronous interface | Bradley Nelson | 2011-08-09 |
| 7885801 | Modeling asynchronous behavior from primary inputs and latches | Zoltan T. Hidvegi, Bradley Nelson | 2011-02-08 |
| 7886244 | Driving values to DC adjusted/untimed nets to identify timing problems | Robert B. Gass, Christoph Jaeschke | 2011-02-08 |
| 7882473 | Sequential equivalence checking for asynchronous verification | Jason R. Baumgartner, Hari Mony, Viresh Paruthi, Barinjato Ramanandray | 2011-02-01 |
| 7877717 | Accurately modeling an asynchronous interface using expanded logic elements | Bing-Lun Chu, Bradley Nelson, Wolfgang Roesner | 2011-01-25 |
| 7870528 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation | Bradley Nelson | 2011-01-11 |
| 7519928 | Method for propagating phase constants in static model analysis of circuits | — | 2009-04-14 |
| 7490305 | Method for driving values to DC adjusted/untimed nets to identify timing problems | Robert B. Gass, Christoph Jaeschke | 2009-02-10 |
| 7484192 | Method for modeling metastability decay through latches in an integrated circuit model | Bradley Nelson | 2009-01-27 |
| 7484196 | Method for asynchronous clock modeling in an integrated circuit simulation | Bradley Nelson | 2009-01-27 |
| 7453759 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Bradley Nelson, Wolfgang Roesner | 2008-11-18 |
| 7447620 | Modeling asynchronous behavior from primary inputs and latches | Zoltan T. Hidvegi, Bradley Nelson | 2008-11-04 |
| 7448015 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation | Bradley Nelson | 2008-11-04 |
| 7302659 | System and method for unfolding/replicating logic paths to facilitate propagation delay modeling | Bradley Nelson | 2007-11-27 |
| 7299436 | System and method for accurately modeling an asynchronous interface using expanded logic elements | Bing-Lun Chu, Bradley Nelson, Wolfgang Roesner | 2007-11-20 |