| 9563548 |
Error injection and error counting during memory scrubbing operations |
Glenn D. Gilda, Patrick J. Meaney |
2017-02-07 |
| 9459997 |
Error injection and error counting during memory scrubbing operations |
Glenn D. Gilda, Patrick J. Meaney |
2016-10-04 |
| 9437327 |
Combined rank and linear address incrementing utility for computer memory test operations |
Patrick J. Meaney, George C. Wellwood |
2016-09-06 |
| 9318171 |
Dual asynchronous and synchronous memory system |
Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson +4 more |
2016-04-19 |
| 9298614 |
Combined rank and linear address incrementing utility for computer memory test operations |
Patrick J. Meaney, George C. Wellwood |
2016-03-29 |
| 9142272 |
Dual asynchronous and synchronous memory system |
Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson +4 more |
2015-09-22 |
| 8688880 |
Centralized serialization of requests in a multiprocessor system |
Garrett M. Drapala, Michael A. Blake, Timothy C. Bronson |
2014-04-01 |
| 8479070 |
Integrated circuit arrangement for test inputs |
Ulrich Baur, Ronald J. Frishmuth, Ralf Ludewig, Ching-Lung Tong, Tobias Webel |
2013-07-02 |
| 8364904 |
Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer |
Michael A. Blake, Garrett M. Drapala, Edward J. Kaminski, Jr., Craig R. Walters |
2013-01-29 |
| 7987400 |
Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy |
Christopher J. Berry, Patrick J. Meaney, Diana L. Orf |
2011-07-26 |
| 7979732 |
Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit |
John M. Isakson, Arjen A. Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen Tucker |
2011-07-12 |
| 7979838 |
Method of automating creation of a clock control distribution network in an integrated circuit floorplan |
Christopher J. Berry, Jose L. Neves, Patrick J. Meaney, Travis W. Pouarz, William J. Scarpero, Jr. |
2011-07-12 |
| 6714826 |
Facility for simultaneously outputting both a mixed digital audio signal and an unmixed digital audio signal multiple concurrently received streams of digital audio data |
James F. Driftmyer, Eric M. Foster |
2004-03-30 |
| 6519283 |
Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics |
Dennis P. Cheney, William Lee, Leland D. Richardson, Ronald S. Svec |
2003-02-11 |
| 6469743 |
Programmable external graphics/video port for digital video decode system chip |
Dennis P. Cheney, William Lee, Leland D. Richardson, Ronald S. Svec |
2002-10-22 |
| 6198772 |
Motion estimation processor for a digital video encoder |
Charles Boice, John M. Kaczmarczyk, Agnes Y. Ngai, Charles Stein |
2001-03-06 |
| 5920359 |
Video encoding method, system and computer program product for optimizing center of picture quality |
Charles Stein, Everett G. Vail, III |
1999-07-06 |
| 5309037 |
Power-on reset circuit with arbitrary output prevention |
Matthew J. Mitchell, Jr. |
1994-05-03 |
