Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9929749 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Mary P. Kusko, Cedric Lichtenau | 2018-03-27 |
| 9923579 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Michael Fee, Mary P. Kusko, Cedric Lichtenau | 2018-03-20 |
| 9915701 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Mary P. Kusko, Cedric Lichtenau | 2018-03-13 |
| 9910090 | Bypassing an encoded latch on a chip during a test-pattern scan | Michael Fee, Mary P. Kusko, Cedric Lichtenau | 2018-03-06 |
| 8479070 | Integrated circuit arrangement for test inputs | Ulrich Baur, Lawrence D. Curley, Ralf Ludewig, Ching-Lung Tong, Tobias Webel | 2013-07-02 |