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Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module |
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Low latency data transfer between clock domains operated in various synchronization modes |
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Integrated circuit arrangement for test inputs |
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Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system |
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Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system |
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Method to prevent firmware defects from disturbing logic clocks to improve system reliability |
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Methods to self-synchronize clocks on multiple chips in a system |
Charlie C. Hwang, Timothy G. McNamara, Wiren D. Becker |
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Measuring microprocessor susceptibility to internal noise generation |
Sungjun Chun, Timothy M. Skergan, Roger D. Weekly |
2007-12-25 |
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Method and apparatus for controlling clocks in a processor with mirrored units |
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2001-12-25 |
