Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10078418 | Hardware management and reconstruction using visual graphics | An Chen | 2018-09-18 |
| 10078970 | Hardware management and reconstruction using visual graphics | An Chen | 2018-09-18 |
| 9679411 | Hardware management and reconstruction using visual graphics | An Chen | 2017-06-13 |
| 9569889 | Hardware management and reconstruction using visual graphics | An Chen | 2017-02-14 |
| 8295419 | Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system | Charlie C. Hwang, Wiren D. Becker, Ching-Lung Tong | 2012-10-23 |
| 8090929 | Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes | Jeffrey A. Magee, Walter Niklaus, Scott Barnett Swaney, Tobias Webel | 2012-01-03 |
| 8001411 | Generating a local clock domain using dynamic controls | Sean Michael Carey, William V. Huott, Christian Jacobi, Guenter Mayer, Chung-Lung K. Shum +2 more | 2011-08-16 |
| 7996715 | Multi nodal computer system and method for handling check stops in the multi nodal computer system | Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Patrick J. Meaney | 2011-08-09 |
| 7826579 | Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system | Charlie C. Hwang, Wiren D. Becker, Ching-Lung Tong | 2010-11-02 |
| 7484118 | Multi nodal computer system and method for handling check stops in the multi nodal computer system | Karin Rebmann, Dietmar Schmunkamp, Tobias Webel, Thomas E. Gilbert, Patrick J. Meaney | 2009-01-27 |
| 7437637 | Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing | Patrick J. Meaney, Bryan L. Mechtly | 2008-10-14 |
| 7382844 | Methods to self-synchronize clocks on multiple chips in a system | Charlie C. Hwang, Ching-Lung Tong, Wiren D. Becker | 2008-06-03 |
| 7368958 | Methods and systems for locally generating non-integral divided clocks with centralized state machines | William V. Huott, Charlie C. Hwang | 2008-05-06 |
| 7355460 | Method for locally generating non-integral divided clocks with centralized state machines | William V. Huott, Charlie C. Hwang | 2008-04-08 |
| 7146520 | Method and apparatus for controlling clocks in a processor with mirrored units | Michael Billeci, Ching-Lung Tong, David A. Webber | 2006-12-05 |
| 7129764 | System and method for local generation of a ratio clock | William V. Huott | 2006-10-31 |
| 7047466 | Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing | Patrick J. Meaney, Bryan L. Mechtly | 2006-05-16 |
| 6990076 | Synchronous bi-directional data transfer having increased bandwidth and scan test features | Bryan J. Robbins, William Robert Reohr | 2006-01-24 |
| 6748565 | System and method for adjusting timing parts | Glenn E. Holmes, William J. Scarpero, Jr. | 2004-06-08 |
| 6629281 | Method and system for at speed diagnostics and bit fail mapping | William V. Huott, Timothy J. Koprowski | 2003-09-30 |
| 6629280 | Method and apparatus for delaying ABIST start | Timothy J. Koprowski, William V. Huott, Pradip Patel | 2003-09-30 |
| 6311313 | X-Y grid tree clock distribution network with tunable tree and grid networks | Peter J. Camporese, Alina Deutsch, Phillip J. Restle, David A. Webber | 2001-10-30 |
| 6205571 | X-Y grid tree tuning method | Peter J. Camporese, Alina Deutsch, Phillip J. Restle, David A. Webber | 2001-03-20 |
| 6195757 | Method for supporting 11/2 cycle data paths via PLL based clock system | Patrick J. Meaney, Paul D. Muench, Giacomo Vincent Ingenio | 2001-02-27 |
| 6125465 | Isolation/removal of faults during LBIST testing | William V. Huott, Timothy J. Koprowski | 2000-09-26 |