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Selective test pattern processor |
Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace |
2016-03-01 |
| 9274172 |
Selective test pattern processor |
Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace |
2016-03-01 |
| 9244756 |
Logic-built-in-self-test diagnostic method for root cause identification |
Donato O. Forlenza, Orazio P. Forlenza |
2016-01-26 |
| 9244757 |
Logic-built-in-self-test diagnostic method for root cause identification |
Donato O. Forlenza, Orazio P. Forlenza |
2016-01-26 |
| 8443313 |
Circuit design optimization |
Samuel I. Ward, Kevin F. Reick, Thomas E. Rosser, Robert J. Shadowen |
2013-05-14 |
| 8386230 |
Circuit design optimization |
Samuel I. Ward, Kevin F. Reick, Thomas E. Rosser, Robert J. Shadowen |
2013-02-26 |
| 8095837 |
Method and apparatus for improving random pattern testing of logic structures |
Mary P. Kusko, Barry W. Krumm, Patrick J. Meaney |
2012-01-10 |
| 7934134 |
Method and apparatus for performing logic built-in self-testing of an integrated circuit |
Donato O. Forlenza, Orazio P. Forlenza, Phong T. Tran |
2011-04-26 |
| 7921346 |
Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD) |
Donato O. Forlenza, Orazio P. Forlenza, Phong T. Tran |
2011-04-05 |
| 7117415 |
Automated BIST test pattern sequence generator software system and method |
Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley |
2006-10-03 |
| 6990076 |
Synchronous bi-directional data transfer having increased bandwidth and scan test features |
Timothy G. McNamara, William Robert Reohr |
2006-01-24 |
| 6836865 |
Method and apparatus for facilitating random pattern testing of logic structures |
Mary P. Kusko, William V. Huott, Timothy Charest |
2004-12-28 |
| 6751765 |
Method and system for determining repeatable yield detractors of integrated circuits |
Richard F. Rizzolo, Rocco E. DeStefano, Joseph Eckelman, Thomas G. Foote, Steven Michnowski +2 more |
2004-06-15 |
| 6671838 |
Method and apparatus for programmable LBIST channel weighting |
Timothy J. Koprowski, Mary P. Kusko, Lawrence K. Lange |
2003-12-30 |
| 6532571 |
Method to improve a testability analysis of a hierarchical design |
Richard M. Gabrielson, Kevin William McCauley, Richard F. Rizzolo, Joseph M. Swenton |
2003-03-11 |
| 6314540 |
Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips |
William V. Huott, Mary P. Kusko, Gregory O'Malley |
2001-11-06 |
