Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7093208 | Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices | Patrick M. Williams, Ee K. Cho, David J. Hathaway, Mei-Ting Hsu, Gregory A. Northrop +3 more | 2006-08-15 |
| 7010763 | Method of optimizing and analyzing selected portions of a digital integrated circuit | David J. Hathaway, Chandramouli Visweswariah, Patrick M. Williams | 2006-03-07 |
| 6671838 | Method and apparatus for programmable LBIST channel weighting | Timothy J. Koprowski, Mary P. Kusko, Bryan J. Robbins | 2003-12-30 |
| 4617664 | Error correction for multiple bit output chips | Frederick J. Aichelmann, Jr. | 1986-10-14 |
| 4506364 | Memory address permutation apparatus | Frederick J. Aichelmann, Jr. | 1985-03-19 |
| 4458349 | Method for storing data words in fault tolerant memory to recover uncorrectable errors | Frederick J. Aichelmann, Jr. | 1984-07-03 |