Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9715420 | String dataflow error detection | James R. Cuffney, John G. Rell, Jr., Patrick M. West, Jr. | 2017-07-25 |
| 9588838 | String dataflow error detection | James R. Cuffney, John G. Rell, Jr., Patrick M. West, Jr. | 2017-03-07 |
| 9389955 | String dataflow error detection | James R. Cuffney, John G. Rell, Jr., Patrick M. West, Jr. | 2016-07-12 |
| 9292398 | Design-based weighting for logic built-in self-test | Gregory J. Cook, Mary P. Kusko, Cedric Lichtenau | 2016-03-22 |
| 9292399 | Design-Based weighting for logic built-in self-test | Gregory J. Cook, Mary P. Kusko, Cedric Lichtenau | 2016-03-22 |
| 6968489 | Pseudo random optimized built-in self-test | Franco Motika | 2005-11-22 |
| 6816990 | VLSI chip test power reduction | Peilin Song, Ulrich Baur, Franco Motika | 2004-11-09 |
| 6708305 | Deterministic random LBIST | L. Farnsworth, Brion Keller, Bernd Koenemann, Thomas J. Snethen, Donald L. Wheater | 2004-03-16 |
| 6671838 | Method and apparatus for programmable LBIST channel weighting | Mary P. Kusko, Lawrence K. Lange, Bryan J. Robbins | 2003-12-30 |
| 6629280 | Method and apparatus for delaying ABIST start | William V. Huott, Timothy G. McNamara, Pradip Patel | 2003-09-30 |
| 6629281 | Method and system for at speed diagnostics and bit fail mapping | Timothy G. McNamara, William V. Huott | 2003-09-30 |
| 6442720 | Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis | Mary P. Kusko, Richard F. Rizzolo, Peilin Song | 2002-08-27 |
| 6442723 | Logic built-in self test selective signature generation | Franco Motika, Phillip J. Nigh | 2002-08-27 |
| 6327685 | Logic built-in self test | Franco Motika | 2001-12-04 |
| 6125465 | Isolation/removal of faults during LBIST testing | Timothy G. McNamara, William V. Huott | 2000-09-26 |
| 6021514 | Limited latch linehold capability for LBIST testing | — | 2000-02-01 |
| 5479414 | Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing | Paul Keller | 1995-12-26 |