| 12050852 |
Signal pre-routing in an integrated circuit design |
Wolfgang Roesner, Ali S. El-Zein, Viresh Paruthi, Stephen G. Shuma, Stephen John Barnfield +1 more |
2024-07-30 |
| 10599804 |
Pin cloning and subway creation on automatically generated design physical hierarchy |
Ali S. El-Zein, Alvan W. Ng, Clay Chip Smith, Wolfgang Roesner |
2020-03-24 |
| 8640065 |
Circuit verification using computational algebraic geometry |
Gradus Janssen, Luis A. Lastras-Montano, Alexey Y. Lvov, Viresh Paruthi, Barry M. Trager +2 more |
2014-01-28 |
| 8453080 |
Model build in the presence of a non-binding reference |
Wolfgang Roesner, Derek E. Williams |
2013-05-28 |
| 8443314 |
Abstraction level-preserving conversion of flip-flop-inferred hardware description language (HDL) to instantiated HDL |
Ali S. El-Zein, Wolfgang Roesner |
2013-05-14 |
| 8443313 |
Circuit design optimization |
Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Thomas E. Rosser |
2013-05-14 |
| 8386230 |
Circuit design optimization |
Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Thomas E. Rosser |
2013-02-26 |
| 7774724 |
Specifying a configuration for a digital system utilizing dial biasing weights |
Bryan Hunt, Wolfgang Roesner, Derek E. Williams |
2010-08-10 |
| 7441209 |
Method, system and program product for providing a configuration specification language supporting error checking dials |
Wolfgang Roesner, Derek E. Williams |
2008-10-21 |
| 7434193 |
Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights |
Bryan Hunt, Wolfgang Roesner, Derek E. Williams |
2008-10-07 |
