Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9298872 | Apportioning synthesis effort for better timing closure | Gi-Joon Nam, Manikandan Viswanath | 2016-03-29 |
| 8638120 | Programmable gate array as drivers for data ports of spare latches | Ashish Jaitly, Sridhar H. Rangarajan | 2014-01-28 |
| 8572536 | Spare latch distribution | George Antony, Sridhar H. Rangarajan | 2013-10-29 |
| 8443313 | Circuit design optimization | Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Robert J. Shadowen | 2013-05-14 |
| 8386230 | Circuit design optimization | Samuel I. Ward, Kevin F. Reick, Bryan J. Robbins, Robert J. Shadowen | 2013-02-26 |
| 8166439 | Techniques for selecting spares to implement a design change in an integrated circuit | Jeremy T. Hopkins | 2012-04-24 |
| 7979732 | Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit | Lawrence D. Curley, John M. Isakson, Arjen A. Mets, Travis W. Pouarz, Kristen Tucker | 2011-07-12 |
| 7979819 | Minterm tracing and reporting | Jeremy T. Hopkins | 2011-07-12 |
| 7552040 | Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects | Barry Lee Dorfman, Jeffrey P. Soreff | 2009-06-23 |
| 7194394 | Method and apparatus for detecting and correcting inaccuracies in curve-fitted models | Barry Lee Dorfman | 2007-03-20 |
| 6922818 | Method of power consumption reduction in clocked circuits | Sam Gat-Shang Chu, Joachim Clabes, Michael N. Goulet, James D. Warnock | 2005-07-26 |
| 6728944 | Method, system, and computer program product for improving wireability near dense clock nets | Joachim Clabes | 2004-04-27 |
| 6654943 | Method, system, and computer program product for correcting anticipated problems related to global routing | Joachim Clabes | 2003-11-25 |
| 6526543 | Method, system, and computer program product for optimizing logic during synthesis of logic designs | — | 2003-02-25 |
| 6460166 | System and method for restructuring of logic circuitry | Lakshmi N. Reddy | 2002-10-01 |
| 6339835 | Pseudo-anding in dynamic logic circuits | Lakshmi N. Reddy | 2002-01-15 |
| 6282695 | System and method for restructuring of logic circuitry | Lakshmi N. Reddy | 2001-08-28 |
| 6035110 | Identifying candidate nodes for phase assignment in a logic network | Ruchir Puri, Andrew A. Bjorksten | 2000-03-07 |
| 6018621 | Identifying an optimizable logic region in a logic network | Ruchir Puri, Andrew A. Bjorksten | 2000-01-25 |
| 5903467 | Selecting phase assignments for candidate nodes in a logic network | Ruchir Puri, Andrew A. Bjorksten | 1999-05-11 |
| 5774369 | Computer program product for enabling a computer to remove redundancies using quasi algebraic methods | Paul William Horstmann, Prashant Sawkar | 1998-06-30 |
| 5524082 | Redundancy removal using quasi-algebraic methods | Paul William Horstmann, Prashant Sawkar | 1996-06-04 |