Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204832 | Logical clock connection in an integrated circuit design | Viresh Paruthi, Alvan W. Ng, Benedikt Geukes, Klaus-Dieter Schubert, Robert Alan Cargnoni +6 more | 2025-01-21 |
| 12050852 | Signal pre-routing in an integrated circuit design | Wolfgang Roesner, Viresh Paruthi, Stephen G. Shuma, Stephen John Barnfield, Alvan W. Ng +1 more | 2024-07-30 |
| 11663381 | Clock mapping in an integrated circuit design | Stephen G. Shuma, Wolfgang Roesner, Viresh Paruthi, Benedikt Geukes, Klaus-Dieter Schubert +3 more | 2023-05-30 |
| 10599804 | Pin cloning and subway creation on automatically generated design physical hierarchy | Robert J. Shadowen, Alvan W. Ng, Clay Chip Smith, Wolfgang Roesner | 2020-03-24 |
| 10565338 | Equivalency verification for hierarchical references | Mark A. Williams, Robert L. Kanzelman, Viresh Paruthi, Wolfgang Roesner | 2020-02-18 |
| 9495496 | Non-invasive insertion of logic functions into a register-transfer level (‘RTL’) design | Stephen John Barnfield | 2016-11-15 |
| 8713494 | Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing | Gabor Bobok, Gabor Drasny | 2014-04-29 |
| 8640065 | Circuit verification using computational algebraic geometry | Gradus Janssen, Luis A. Lastras-Montano, Alexey Y. Lvov, Viresh Paruthi, Robert J. Shadowen +2 more | 2014-01-28 |
| 8495533 | Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing | Gabor Drasny, Gabor Bobok | 2013-07-23 |
| 8443314 | Abstraction level-preserving conversion of flip-flop-inferred hardware description language (HDL) to instantiated HDL | Wolfgang Roesner, Robert J. Shadowen | 2013-05-14 |
| 8439784 | Braking system | — | 2013-05-14 |
| 8234604 | Co-optimization of embedded systems utilizing symbolic execution | Fadi A. Zaraket | 2012-07-31 |
| 8230406 | Compiler option consistency checking during incremental hardware design language compilation | Richard L. H. Carbone, Gabor Bobok, Gabor Drasny | 2012-07-24 |
| 8140313 | Techniques for modeling variables in subprograms of hardware description language programs | Gabor Drasny, Wolfgang Roesner, Fadi A. Zaraket | 2012-03-20 |
| 8141048 | Sequential encoding for relational analysis (SERA) of a software model | Jason R. Baumgartner, Viresh Paruthi, Fadi A. Zaraket | 2012-03-20 |
| 7823097 | Unrolling hardware design generate statements in a source window debugger | Gabor Drasny, Gabor Bobok, Fadi A. Zaraket | 2010-10-26 |
| 7506287 | Method, system, and program product for pre-compile processing of hardware design language (HDL) source files | Gabor Drasny, Gabor Bobok, Fadi A. Zaraket, Hussein Sharafeddin | 2009-03-17 |
| 7284210 | Method for reconfiguration of random biases in a synthesized design without recompilation | Jason R. Baumgartner, Daniel Heller, Wolfgang Roesner | 2007-10-16 |