Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9286426 | Method and apparatus for testing | Shlomit Koyfman, Shiri Moran, Ziv Nevo, Gil Eliezer Shurek | 2016-03-15 |
| 8713494 | Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing | Gabor Drasny, Ali S. El-Zein | 2014-04-29 |
| 8495533 | Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing | Gabor Drasny, Ali S. El-Zein | 2013-07-23 |
| 8407641 | Logic design verification techniques for liveness checking with retiming | Jason R. Baumgartner, Paul Joseph Roessler, Mark A. Williams | 2013-03-26 |
| 8255848 | Logic design verification techniques for liveness checking with retiming | Jason R. Baumgartner, Paul Joseph Roessler, Mark A. Williams | 2012-08-28 |
| 8230406 | Compiler option consistency checking during incremental hardware design language compilation | Richard L. H. Carbone, Gabor Drasny, Ali S. El-Zein | 2012-07-24 |
| 8160857 | Selective compilation of a simulation model in view of unavailable higher level signals | Wolfgang Roesner, Derek E. Williams | 2012-04-17 |
| 8108199 | Phase events in a simulation model of a digital system | Wolfgang Roesner, Derek E. Williams | 2012-01-31 |
| 7912694 | Print events in the simulation of a digital system | Wolfgang Roesner, Derek E. Williams | 2011-03-22 |
| 7823097 | Unrolling hardware design generate statements in a source window debugger | Gabor Drasny, Ali S. El-Zein, Fadi A. Zaraket | 2010-10-26 |
| 7711537 | Signals for simulation result viewing | Wolfgang Roesner, Derek E. Williams | 2010-05-04 |
| 7617085 | Program product supporting specification of signals for simulation result viewing | Wolfgang Roesner, Derek E. Williams | 2009-11-10 |
| 7552043 | Method, system and program product for selectively removing instrumentation logic from a simulation model | Wolfgang Roesner, Matyas A. Sustik, Derek E. Williams | 2009-06-23 |
| 7506287 | Method, system, and program product for pre-compile processing of hardware design language (HDL) source files | Gabor Drasny, Ali S. El-Zein, Fadi A. Zaraket, Hussein Sharafeddin | 2009-03-17 |
| 7493248 | Method, system and program product supporting phase events in a simulation model of a digital system | Wolfgang Roesner, Derek E. Williams | 2009-02-17 |