Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10990725 | Clock-gating phase algebra for clock analysis | Gavin B. Meil | 2021-04-27 |
| 10599792 | Circuit design analyzer | Gavin B. Meil | 2020-03-24 |
| 10558782 | Phase algebra for virtual clock and mode extraction in hierarchical designs | Gavin B. Meil | 2020-02-11 |
| 10552558 | Conditional phase algebra for clock analysis | Gavin B. Meil | 2020-02-04 |
| 10552559 | Glitch-aware phase algebra for clock analysis | Gavin B. Meil | 2020-02-04 |
| 10515164 | Clock-gating phase algebra for clock analysis | Gavin B. Meil | 2019-12-24 |
| 10503856 | Phase algebra for specifying clocks and modes in hierarchical designs | Gavin B. Meil | 2019-12-10 |
| 10331822 | Clock-gating phase algebra for clock analysis | Gavin B. Meil | 2019-06-25 |
| 10325040 | Conditional phase algebra for clock analysis | Gavin B. Meil | 2019-06-18 |
| 10325041 | Circuit design analyzer | Gavin B. Meil | 2019-06-18 |
| 10318695 | Phase algebra for virtual clock and mode extraction in hierarchical designs | Gavin B. Meil | 2019-06-11 |
| 10216881 | Phase algebra for analysis of hierarchical designs | Gavin B. Meil | 2019-02-26 |
| 9916407 | Phase algebra for analysis of hierarchical designs | Gavin B. Meil | 2018-03-13 |
| 9830412 | Glitch-aware phase algebra for clock analysis | Gavin B. Meil | 2017-11-28 |
| 9798844 | Phase algebra for analysis of hierarchical designs | Gavin B. Meil | 2017-10-24 |
| 9547732 | Static checking of asynchronous clock domain crossings | Gavin B. Meil | 2017-01-17 |
| 9536024 | Methods for static checking of asynchronous clock domain crossings | Gavin B. Meil | 2017-01-03 |
| 9251304 | Circuit design evaluation with compact multi-waveform representations | Gavin B. Meil | 2016-02-02 |
| 8713494 | Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing | Gabor Bobok, Ali S. El-Zein | 2014-04-29 |
| 8495533 | Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing | Gabor Bobok, Ali S. El-Zein | 2013-07-23 |
| 8230406 | Compiler option consistency checking during incremental hardware design language compilation | Richard L. H. Carbone, Gabor Bobok, Ali S. El-Zein | 2012-07-24 |
| 8140313 | Techniques for modeling variables in subprograms of hardware description language programs | Ali S. El-Zein, Wolfgang Roesner, Fadi A. Zaraket | 2012-03-20 |
| 7823097 | Unrolling hardware design generate statements in a source window debugger | Gabor Bobok, Ali S. El-Zein, Fadi A. Zaraket | 2010-10-26 |
| 7506287 | Method, system, and program product for pre-compile processing of hardware design language (HDL) source files | Gabor Bobok, Ali S. El-Zein, Fadi A. Zaraket, Hussein Sharafeddin | 2009-03-17 |
| 7280055 | Method and apparatus for encoding binary data as a zero terminated string | — | 2007-10-09 |