Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907634 | Automating addition of power supply rails, fences, and level translators to a modular circuit design | Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine | 2024-02-20 |
| 10990725 | Clock-gating phase algebra for clock analysis | Gabor Drasny | 2021-04-27 |
| 10599792 | Circuit design analyzer | Gabor Drasny | 2020-03-24 |
| 10558782 | Phase algebra for virtual clock and mode extraction in hierarchical designs | Gabor Drasny | 2020-02-11 |
| 10552558 | Conditional phase algebra for clock analysis | Gabor Drasny | 2020-02-04 |
| 10552559 | Glitch-aware phase algebra for clock analysis | Gabor Drasny | 2020-02-04 |
| 10515164 | Clock-gating phase algebra for clock analysis | Gabor Drasny | 2019-12-24 |
| 10503856 | Phase algebra for specifying clocks and modes in hierarchical designs | Gabor Drasny | 2019-12-10 |
| 10331822 | Clock-gating phase algebra for clock analysis | Gabor Drasny | 2019-06-25 |
| 10325040 | Conditional phase algebra for clock analysis | Gabor Drasny | 2019-06-18 |
| 10325041 | Circuit design analyzer | Gabor Drasny | 2019-06-18 |
| 10318695 | Phase algebra for virtual clock and mode extraction in hierarchical designs | Gabor Drasny | 2019-06-11 |
| 10216881 | Phase algebra for analysis of hierarchical designs | Gabor Drasny | 2019-02-26 |
| 10031987 | Verification of untimed nets | — | 2018-07-24 |
| 9916407 | Phase algebra for analysis of hierarchical designs | Gabor Drasny | 2018-03-13 |
| 9830412 | Glitch-aware phase algebra for clock analysis | Gabor Drasny | 2017-11-28 |
| 9798844 | Phase algebra for analysis of hierarchical designs | Gabor Drasny | 2017-10-24 |
| 9547732 | Static checking of asynchronous clock domain crossings | Gabor Drasny | 2017-01-17 |
| 9536024 | Methods for static checking of asynchronous clock domain crossings | Gabor Drasny | 2017-01-03 |
| 9268889 | Verification of asynchronous clock domain crossings | — | 2016-02-23 |
| 9251304 | Circuit design evaluation with compact multi-waveform representations | Gabor Drasny | 2016-02-02 |
| 9223916 | Timing analysis of asynchronous clock domain crossings | Jack DiLullo | 2015-12-29 |
| 8407451 | Method and apparatus for enabling resource allocation identification at the instruction level in a processor system | Steven L. Roberts, Christopher J. Spandikow | 2013-03-26 |
| 8244979 | System and method for cache-locking mechanism using translation table attributes for replacement class ID determination | Adam P. Burns, Jason N. Dale, Jonathan James DeMent | 2012-08-14 |
| 8122410 | Specifying and validating untimed nets | Jack DiLullo, Ronald Nick Kalla, Jeffrey M. Ritzinger | 2012-02-21 |