Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10565338 | Equivalency verification for hierarchical references | Ali S. El-Zein, Robert L. Kanzelman, Viresh Paruthi, Wolfgang Roesner | 2020-02-18 |
| 8407641 | Logic design verification techniques for liveness checking with retiming | Jason R. Baumgartner, Gabor Bobok, Paul Joseph Roessler | 2013-03-26 |
| 8255848 | Logic design verification techniques for liveness checking with retiming | Jason R. Baumgartner, Gabor Bobok, Paul Joseph Roessler | 2012-08-28 |
| 8201118 | Method and system for dynamic automated hint generation for enhanced reachability analysis | Jason R. Baumgartner, Paul Joseph Roessler, Jiazhao Xu | 2012-06-12 |
| 8042078 | Enhancing formal design verification by reusing previous results | Viresh Paruthi, Travis W. Pouarz | 2011-10-18 |
| 7210109 | Equivalence checking of scan path flush operations | Kenneth Michael Caron, Robert L. Kanzelman, Scott Mack, Lance G. Thompson | 2007-04-24 |
| 6993734 | Use of time step information in a design verification system | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2006-01-31 |