Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8352894 | Verification techniques for liveness checking of logic designs | Jason R. Baumgartner, Paul Joseph Roessler, Ohad Shacham | 2013-01-08 |
| 8201118 | Method and system for dynamic automated hint generation for enhanced reachability analysis | Jason R. Baumgartner, Paul Joseph Roessler, Mark A. Williams | 2012-06-12 |
| 7856609 | Using constraints in design verification | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2010-12-21 |
| 7853917 | System for building binary decision diagrams efficiently in a structural network representation of a digital circuit | Viresh Paruthi, Christian Jacobi, Geert Janssen, Kai Weber | 2010-12-14 |
| 7836413 | Building binary decision diagrams efficiently in a structural network representation of a digital circuit | Viresh Paruthi, Christian Jacobi, Geert Janssen, Kai Weber | 2010-11-16 |
| 7788615 | Computer program product for verification using reachability overapproximation | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2010-08-31 |
| 7739635 | Conjunctive BDD building and variable quantification using case-splitting | Jason R. Baumgartner, Christian Jacobi, Viresh Paruthi | 2010-06-15 |
| 7475370 | System for verification using reachability overapproximation | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2009-01-06 |
| 7421669 | Using constraints in design verification | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-09-02 |
| 7340473 | Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit | Viresh Paruthi, Christian Jacobi, Geert Janssen, Kai Weber | 2008-03-04 |
| 7322017 | Method for verification using reachability overapproximation | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-01-22 |
| 7203915 | Method for retiming in the presence of verification constraints | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2007-04-10 |