Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8734006 | Calibration of an on-die thermal sensor | James M. Crafts, Joseph E. Dery, Timothy C. Taylor | 2014-05-27 |
| 8365006 | Preventing circumvention of function disablement in an information handling system | Steven M. Douskey, Thomas Pflueger, Edward M. Seymour | 2013-01-29 |
| 8281279 | Creating scan chain definition from high-level model using high-level model simulation | William B. Maloney | 2012-10-02 |
| 8090823 | Providing low-level hardware access to in-band and out-of-band firmware | James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin F. Reick +1 more | 2012-01-03 |
| 8086925 | Method and system for LBIST testing of an electronic circuit | Benjamin Robert Gass, Abel Alaniz, Asher Shlomo Lazarus | 2011-12-27 |
| 7916722 | Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor | James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin F. Reick +1 more | 2011-03-29 |
| 7895490 | Method and system for testing an electronic circuit to identify multiple defects | Benjamin Robert Gass, Abel Alaniz, Asher Shlomo Lazarus | 2011-02-22 |
| 7856582 | Techniques for logic built-in self-test diagnostics of integrated circuit devices | Daniel W. Cervantes, Robert B. Gass, Joshua P. Hernandez | 2010-12-21 |
| 7696979 | Method and system for manipulating a plurality of graphical pointers | — | 2010-04-13 |
| 7519889 | System and method to reduce LBIST manufacturing test time of integrated circuits | Daniel W. Cervantes, Joshua P. Hernandez, Tung Nguyen Pham | 2009-04-14 |
| 7467204 | Method for providing low-level hardware access to in-band and out-of-band firmware | James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin F. Reick +1 more | 2008-12-16 |
| 7418541 | Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor | James Stephen Fields, Jr., Paul Frank Lecocq, Brian Chan Monwai, Thomas Pflueger, Kevin F. Reick +1 more | 2008-08-26 |
| 7400555 | Built in self test circuit for measuring total timing uncertainty in a digital data path | Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle | 2008-07-15 |
| 7313747 | Measuring microprocessor susceptibility to internal noise generation | Sungjun Chun, Ching-Lung Tong, Roger D. Weekly | 2007-12-25 |
| 7073106 | Test method for guaranteeing full stuck-at-fault coverage of a memory array | Jose Angel Paredes, Philip G. Shephard, III, Neil Ray Vanderschaaf | 2006-07-04 |
| 6748563 | Method and apparatus for testing path delays in a high-speed boundary scan implementation | Johnny LeBlanc | 2004-06-08 |
| 6665828 | Globally distributed scan blocks | Ravi Kumar Arimilli, Roger N. Bailey, Johnny LeBlanc | 2003-12-16 |
| 6654917 | Method and apparatus for scanning free-running logic | Michael Stephen Floyd, Kevin F. Reick | 2003-11-25 |
| 6550020 | Method and system for dynamically configuring a central processing unit with multiple processing cores | Michael Stephen Floyd, Kevin F. Reick | 2003-04-15 |
| 6539491 | Method and apparatus for implementing IEEE 1149.1 compliant boundary scan | Johnny LeBlanc | 2003-03-25 |
| 6452435 | Method and apparatus for scanning and clocking chips with a high-speed free running clock in a manufacturing test environment | Johnny LeBlanc | 2002-09-17 |
| 6333653 | System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks | Michael Stephen Floyd, Kevin F. Reick | 2001-12-25 |
| 6226345 | High speed clock having a programmable run length | — | 2001-05-01 |
| 6085288 | Dual cache directories with respective queue independently executing its content and allowing staggered write operations | Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis | 2000-07-04 |
| 6023746 | Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction | Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis | 2000-02-08 |