Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8484007 | Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model | Michael P. Mullen, Vasantha R. Vuyyuru, Robert J. Adkins | 2013-07-09 |
| 7996203 | Method, system, and computer program product for out of order instruction address stride prefetch performance verification | Dean G. Bair, Christopher A. Krygowski, Chung-Lung K. Shum | 2011-08-09 |
| 7720669 | Method, system and computer program product for register management in a simulation environment | William J. Lewis | 2010-05-18 |
| 7559002 | Multi-thread parallel segment scan simulation of chip element performance | Dean G. Bair, Thomas Ruane, William J. Lewis | 2009-07-07 |
| 7509552 | Multi-thread parallel segment scan simulation of chip element performance | Dean G. Blair, Thomas Ruane, William J. Lewis | 2009-03-24 |
| 7502725 | Method, system and computer program product for register management in a simulation environment | William J. Lewis | 2009-03-10 |
| 6625117 | Method and apparatus for switching messages from a primary message channel to a secondary message channel in a message queuing system | Shawfu Chen, Robert O. Dryfoos, Allan Feldman, David Hu, Peter A. Lewis +1 more | 2003-09-23 |