HU

Hanno Ulrich

IBM: 12 patents #9,222 of 70,183Top 15%
Overall (All Time): #413,300 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10572304 Dual/multi-mode processor pipelines sampling Deanna Postles Dunn Berger, Kathryn Marie Jackson, Joshua D. Massover, Gary E. Strait, Craig R. Walters 2020-02-25
10572385 Granting exclusive cache access using locality cache coherency state Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova 2020-02-25
10176013 Dual/multi-mode processor pipeline sampling Deanna Postles Dunn Berger, Kathryn Marie Jackson, Joshua D. Massover, Gary E. Strait, Craig R. Walters 2019-01-08
9852071 Granting exclusive cache access using locality cache coherency state Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova 2017-12-26
9798663 Granting exclusive cache access using locality cache coherency state Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova 2017-10-24
9372805 Operating on translation look-aside buffers in a multiprocessor environment Lisa C. Heller, Norbert Hagspiel, Ute Gaertner, Rebecca S. Wisniewski 2016-06-21
8850129 Memory ordered store system in a multiprocessor computer system Norbert Hagspiel, Matthias Klein, Ulrich Mayer, Robert J. Sonnelitter, III, Gary E. Strait 2014-09-30
8572624 Providing multiple quiesce state machines in a computing environment Lisa C. Heller, Norbert Hagspiel, Ute Gaertner, Rebecca S. Wisniewski 2013-10-29
8566529 Method, system and computer program product for generalized LRU in cache and memory performance analysis and modeling David S. Hutton, Keith N. Langston, Kathryn Marie Jackson, Craig R. Walters 2013-10-22
8090883 Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance Gary E. Strait, Mark A. Check, Hong Deng, Diana L. Orf 2012-01-03
7324934 Feedback process to model CP utilization in multi-processor performance models 2008-01-29
7174426 Interleave pre-checking in front of shared caches with pipelined access 2007-02-06