Issued Patents All Time
Showing 25 most recent of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11687148 | Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS | Kevin Tien, Yutaka Nakamura, Jeffrey H. Derby, Martin Cochet, Todd E. Takken +1 more | 2023-06-27 |
| 11295201 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla +3 more | 2022-04-05 |
| 11095313 | Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures | Jeffrey H. Derby, Bruce M. Fleischer, Prashant Jayaprakash Nair | 2021-08-17 |
| 11061675 | Vector cross-compare count and sequence instructions | Jeffrey H. Derby, Dheeraj Sreedhar | 2021-07-13 |
| 10810487 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2020-10-20 |
| 10628732 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2020-04-21 |
| 10564964 | Vector cross-compare count and sequence instructions | Jeffrey H. Derby, Dheeraj Sreedhar | 2020-02-18 |
| 10534608 | Local computation logic embedded in a register file to accelerate programs | Pradip Bose, Alper Buyuktosunoglu, Jeffrey H. Derby, Michele M. Franceschini, Augusto J. Vega | 2020-01-14 |
| 10331998 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla +3 more | 2019-06-25 |
| 10248419 | In-memory/register vector radix sort | Jeffrey H. Derby, Dheeraj Sreedhar | 2019-04-02 |
| 10042876 | Sort-merge-join on a large architected register file | Jeffrey H. Derby, Dheeraj Sreedhar | 2018-08-07 |
| 9887623 | Efficient voltage conversion | Leland Chang, Jae-sun Seo, Albert M. Young | 2018-02-06 |
| 9875328 | High-speed latch circuits by selective use of large gate pitch | Leland Chang | 2018-01-23 |
| 9818058 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla +3 more | 2017-11-14 |
| 9817612 | High-performance hash joins using memory with extensive internal parallelism | Jeffrey H. Derby, Charles L. Johnson, Dheeraj Sreedhar, Steven Paul VanderWiel | 2017-11-14 |
| 9811287 | High-performance hash joins using memory with extensive internal parallelism | Jeffrey H. Derby, Charles L. Johnson, Dheeraj Sreedhar, Steven Paul VanderWiel | 2017-11-07 |
| 9792209 | Method and apparatus for cache memory data processing | Edgar R. Cordero, David M. Daly, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary | 2017-10-17 |
| 9755506 | Efficient voltage conversion | Leland Chang, Jae-sun Seo, Albert M. Young | 2017-09-05 |
| 9740659 | Merging and sorting arrays on an SIMD processor | Dheeraj Sreedhar, Jeffrey H. Derby | 2017-08-22 |
| 9710381 | Method and apparatus for cache memory data processing | Edgar R. Cordero, David M. Daly, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary | 2017-07-18 |
| 9496854 | High-speed latch circuits by selective use of large gate pitch | Leland Chang | 2016-11-15 |
| 9460383 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2016-10-04 |
| 9373073 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla +3 more | 2016-06-21 |
| 9281821 | Time division multiplexed limited switch dynamic logic | Leland Chang, Yutaka Nakamura | 2016-03-08 |
| 9276580 | Time division multiplexed limited switch dynamic logic | Leland Chang, Yutaka Nakamura | 2016-03-01 |