Issued Patents All Time
Showing 26–50 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9239984 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Paul A. Merolla +3 more | 2016-01-19 |
| 9160533 | Random number generation | James R. Kozlosk, Raquel Norel, John J. Rice | 2015-10-13 |
| 9148281 | Random number generation | James R. Kozlosk, Raquel Norel, John J. Rice | 2015-09-29 |
| 9093151 | Programmable regular expression and context free grammar matcher | Richard F. Freitas, Rajendra Shinde | 2015-07-28 |
| 9030235 | Time division multiplexed limited switch dynamic logic | Leland Chang, Yutaka Nakamura | 2015-05-12 |
| 9030234 | Time division multiplexed limited switch dynamic logic | Leland Chang, Yutaka Nakamura | 2015-05-12 |
| 8943374 | Writing scheme for phase change material-content addressable memory | Chung H. Lam, Jing Li | 2015-01-27 |
| 8928295 | Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (IC) chip including the circuit and method of switching voltage on chip | Leland Chang, Jae-sun Seo | 2015-01-06 |
| 8918623 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2014-12-23 |
| 8902690 | Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming | Kailash Gopalakrishnan, Chung H. Lam, Jing Li | 2014-12-02 |
| 8898097 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2014-11-25 |
| 8893079 | Methods for generating code for an architecture encoding an extended register specification | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2014-11-18 |
| 8892487 | Electronic synapses for reinforcement learning | Leland Chang, Dharmendra S. Modha | 2014-11-18 |
| 8893095 | Methods for generating code for an architecture encoding an extended register specification | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2014-11-18 |
| 8856055 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu +4 more | 2014-10-07 |
| 8842491 | Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming | Kailash Gopalakrishnan, Chung H. Lam, Jing Li | 2014-09-23 |
| 8837198 | Multi-bit resistance measurement | Chung H. Lam, Jing Li | 2014-09-16 |
| 8687398 | Sense scheme for phase change material content addressable memory | Leland Chang, Chung H. Lam, Jing Li | 2014-04-01 |
| 8661072 | Shared parallel adder tree for executing multiple different population count operations | Bartholomew Blaner, Todd R. Iglehart | 2014-02-25 |
| 8638598 | Multi-bit resistance measurement | Chung H. Lam, Jing Li | 2014-01-28 |
| 8629705 | Low voltage signaling | Leland Chang, Robert H. Dennard, Brian L. Ji, Wing K. Luk | 2014-01-14 |
| 8604832 | Time division multiplexed limited switch dynamic logic | Leland Chang, Yutaka Nakamura | 2013-12-10 |
| 8605489 | Enhanced data retention mode for dynamic memories | William Robert Reohr, Michael A. Sperling | 2013-12-10 |
| 8560902 | Writing scheme for phase change material-content addressable memory | Chung H. Lam, Jing Li | 2013-10-15 |
| 8555119 | Test structure for characterizing multi-port static random access memory and register file arrays | Leland Chang, Jente B. Kuang, Hung C. Ngo, Kevin John Nowka | 2013-10-08 |