Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8493093 | Time division multiplexed limited switch dynamic logic | Leland Chang, Yutaka Nakamura | 2013-07-23 |
| 8446748 | Content addressable memories with wireline compensation | Chung H. Lam, Jing Li | 2013-05-21 |
| 8395438 | Switched capacitor voltage converters | Robert H. Dennard, Brian L. Ji | 2013-03-12 |
| 8312424 | Methods for generating code for an architecture encoding an extended register specification | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2012-11-13 |
| 8295056 | Silicon carrier structure and method of forming same | Paul S. Andry, Harm Peter Hofstee, George A. Katopis, John U. Knickerbocker, Chirag S. Patel | 2012-10-23 |
| 8261138 | Test structure for characterizing multi-port static random access memory and register file arrays | Leland Chang, Jente B. Kuang, Hung C. Ngo, Kevin John Nowka | 2012-09-04 |
| 8248152 | Switched capacitor voltage converters | Robert H. Dennard, Brian L. Ji | 2012-08-21 |
| 8166281 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2012-04-24 |
| 8120937 | Ternary content addressable memory using phase change devices | Brian L. Ji, Chung H. Lam, Bipin Rajendran | 2012-02-21 |
| 8107276 | Resistive memory devices having a not-and (NAND) structure | Matthew J. Breitwisch, Gary S. Ditlow, Michele M. Franceschini, Luis A. Lastras-Montano, Bipin Rajendran | 2012-01-31 |
| 8059438 | Content addressable memory array programmed to perform logic operations | Leland Chang, Gary S. Ditlow, Brian L. Ji | 2011-11-15 |
| 8054662 | Content addressable memory array | Leland Chang, Gary S. Ditlow, Brian L. Ji | 2011-11-08 |
| 8020073 | Dynamic memory architecture employing passive expiration of data | Philip G. Emma, William Robert Reohr | 2011-09-13 |
| 7948782 | Content addressable memory reference clock | Leland Chang, Gary S. Ditlow, Brian L. Ji | 2011-05-24 |
| 7839715 | SerDes double rate bitline with interlock to block precharge capture | Leland Chang, Gary S. Ditlow, Salvatore N. Storino | 2010-11-23 |
| 7793081 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2010-09-07 |
| 7751217 | Content addressable memory using phase change devices | Chung H. Lam, Brian L. Ji, Bipin Rajendran | 2010-07-06 |
| 7668024 | Hybrid static and dynamic sensing for memory arrays | Leland Chang, Yutaka Nakamura | 2010-02-23 |
| 7631167 | System for SIMD-oriented management of register maps for map-based indirect register-file access | Peter G. Capek, Jeffrey H. Derby | 2009-12-08 |
| 7526610 | Sectored cache memory | Philip G. Emma, Vijayalakshmi Srinivasan | 2009-04-28 |
| 7501850 | Scannable limited switch dynamic logic (LSDL) circuit | Anthony Correale, Jr., Thomas Anderson Dick, Sven Meier | 2009-03-10 |
| 7472226 | Methods involving memory caches | Philip G. Emma, Vijayalakshmi Srinivasan | 2008-12-30 |
| 7461209 | Transient cache storage with discard function for disposable data | Erik R. Altman, Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman +1 more | 2008-12-02 |
| 7421566 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Brett Olsson, John-David Wellman | 2008-09-02 |
| 7383480 | Scanning latches using selecting array | Andrew K. Martin, Chandler McDowell, Jun Sawada | 2008-06-03 |