Issued Patents All Time
Showing 76–100 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7360063 | Method for SIMD-oriented management of register maps for map-based indirect register-file access | Peter G. Capek, Jeffrey H. Derby | 2008-04-15 |
| 7349288 | Ultra high-speed Nor-type LSDL/Domino combined address decoder | Yutaka Nakamura | 2008-03-25 |
| 7337202 | Shift-and-negate unit within a fused multiply-adder circuit | Ramyanshu Datta | 2008-02-26 |
| 7298193 | Methods and arrangements to adjust a duty cycle | Kanak B. Agarwal | 2007-11-20 |
| 7290203 | Dynamic memory architecture employing passive expiration of data | Philip G. Emma, William Robert Reohr | 2007-10-30 |
| 7282960 | Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock | Wendy A. Belluomini, Aniket Mukul Saha | 2007-10-16 |
| 7284029 | 4-to-2 carry save adder using limited switching dynamic logic | Wendy A. Belluomini, Ramyanshu Datta, Chandler McDowell, Hung C. Ngo | 2007-10-16 |
| 7242629 | High speed latch circuits using gated diodes | Wing K. Luk, Leland Chang, Robert H. Dennard | 2007-07-10 |
| 7216141 | Computing carry-in bit to most significant bit carry save adder in current stage | Wendy A. Belluomini, Ramyanshu Datta, Jente B. Kuang, Chandler McDowell, Hung C. Ngo | 2007-05-08 |
| 7129754 | Controlled load limited switch dynamic logic circuitry | Hung C. Ngo, Jayakumaran Sivagnaname, Kevin John Nowka | 2006-10-31 |
| 7116594 | Sense amplifier circuits and high speed latch circuits using gated diodes | Wing K. Luk, Leland Chang, Robert H. Dennard | 2006-10-03 |
| 7106620 | Memory cell having improved read stability | Leland Chang, Robert H. Dennard | 2006-09-12 |
| 7047468 | Method and apparatus for low overhead circuit scan | Wendy A. Belluomini, Andrew K. Martin, Chandler McDowell | 2006-05-16 |
| 7014122 | Method and apparatus for performing bit-aligned permute | Ramyanshu Datta | 2006-03-21 |
| 6952352 | Integrated circuit chip package with formable intermediate 3D wiring structure | Philip G. Emma, Arthur R. Zingher | 2005-10-04 |
| 6891399 | Variable pulse width and pulse separation clock generator | Hung C. Ngo, Wendy A. Belluomini | 2005-05-10 |
| 6873188 | Limited switch dynamic logic selector circuits | Wendy A. Belluomini, Hung C. Ngo | 2005-03-29 |
| 6763432 | Cache memory system for selectively storing directory information for a higher level cache in portions of a lower level cache | Mark J. Charney, Philip G. Emma, Arthur R. Zingher | 2004-07-13 |
| 6690204 | Limited switch dynamic logic circuit | Wendy A. Belluomini, Hung C. Ngo | 2004-02-10 |
| 6667555 | Spacer-connector stud for stacked surface laminated multi-chip modules and methods of manufacture | David L. Cohn, Dennis McBride | 2003-12-23 |
| 6650145 | Circuits and systems for limited switch dynamic logic | Hung C. Ngo, Wendy A. Belluomini | 2003-11-18 |
| 6618506 | Method and apparatus for improved compression and decompression | Daniel Auerbach, Timothy Michael Kemp, John Palmer | 2003-09-09 |
| 6573758 | Fast, symmetrical XOR/XNOR gate | David William Boerstler, Juan-Antonio Carballo | 2003-06-03 |
| 6537852 | Spacer - connector stud for stacked surface laminated multichip modules and methods of manufacture | David L. Cohn, Dennis McBride | 2003-03-25 |
| 6507115 | Multi-chip integrated circuit module | Harm Peter Hofstee, Edmund J. Sprogis | 2003-01-14 |