Issued Patents All Time
Showing 25 most recent of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406186 | Conflict-free, stall-free, broadcast network on chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Dharmendra S. Modha, Michael Vincent DeBole +2 more | 2025-09-02 |
| 12406174 | Multi-agent instruction execution engine for neural inference processing | Andrew S. Cassidy, Simon James Hollis, Hartmut Penner, Pallab Datta, John V. Arthur | 2025-09-02 |
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Myron D. Flickner, Andrew S. Cassidy, John V. Arthur, Pallab Datta, Dharmendra S. Modha +6 more | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Pallab Datta, Andrew S. Cassidy, Myron D. Flickner, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2025-08-12 |
| 12182687 | Data representation for dynamic precision in neural network cores | John V. Arthur, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | John V. Arthur, Brian Taba, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2023-12-19 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, Dharmendra S. Modha, John V. Arthur, Andrew S. Cassidy, Rathinakumar Appuswamy +5 more | 2023-05-30 |
| 11537859 | Flexible precision neural inference processing unit | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steve Esser +4 more | 2022-12-27 |
| 11521085 | Neural network weight distribution from a grid of memory elements | Dharmendra S. Modha, Andrew S. Cassidy, John V. Arthur, Tapan K. Nayak, Carlos O. Otero +3 more | 2022-12-06 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2022-11-15 |
| 11270196 | Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine | Filipp A. Akopyan, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta +5 more | 2022-03-08 |
| 11263011 | Compound instruction set architecture for a neural inference chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Michael Vincent DeBole +5 more | 2022-03-01 |
| 11238347 | Data distribution in an array of neural network cores | Brian Taba, Andrew S. Cassidy, Myron D. Flickner, Pallab Datta, Hartmut Penner +5 more | 2022-02-01 |
| 11184221 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +1 more | 2021-11-23 |
| 11049001 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +1 more | 2021-06-29 |
| 11010662 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2021-05-18 |
| 10990872 | Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency | Filipp A. Akopyan, Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Steven K. Esser +3 more | 2021-04-27 |
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +2 more | 2021-04-20 |
| 10929747 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +1 more | 2021-02-23 |
| 10838860 | Memory-mapped interface to message-passing computing systems | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Michael Vincent DeBole, Paul A. Merolla +1 more | 2020-11-17 |
| 10831595 | Performing error detection during deterministic program execution | Andrew S. Cassidy, Dharmendra S. Modha, John V. Arthur | 2020-11-10 |
| 10834024 | Selective multicast delivery on a bus-based interconnect | Simon James Hollis, Hartmut Penner, Andrew S. Cassidy, Pallab Datta | 2020-11-10 |