Issued Patents All Time
Showing 25 most recent of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400109 | Functional synthesis of networks of neurosynaptic cores on neuromorphic substrates | Andrew S. Cassidy, Pallab Datta, Dharmendra S. Modha | 2025-08-26 |
| 12400112 | Efficient method for VLSI implementation of useful neural network activation functions | Jun Sawada, Andrew S. Cassidy, John V. Arthur, Pallab Datta, Dharmendra S. Modha +6 more | 2025-08-26 |
| 12387082 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Pallab Datta, Andrew S. Cassidy, Hartmut Penner, Rathinakumar Appuswamy, Jun Sawada +5 more | 2025-08-12 |
| 12260316 | Automatic timing resolution among neural network components | Pallab Datta, Dharmendra S. Modha | 2025-03-25 |
| 12182687 | Data representation for dynamic precision in neural network cores | John V. Arthur, Andrew S. Cassidy, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2024-12-31 |
| 12165050 | Networks for distributing parameters and data to neural network compute cores | John V. Arthur, Brian Taba, Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta +5 more | 2024-12-10 |
| 12067472 | Defect resistant designs for location-sensitive neural network processor arrays | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2024-08-20 |
| 12056598 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2024-08-06 |
| 11847553 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Andrew S. Cassidy, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy, Jun Sawada +5 more | 2023-12-19 |
| 11663461 | Instruction distribution in an array of neural network cores | Hartmut Penner, Dharmendra S. Modha, John V. Arthur, Andrew S. Cassidy, Rathinakumar Appuswamy +5 more | 2023-05-30 |
| 11636317 | Long-short term memory (LSTM) cells on spiking neuromorphic hardware | Rathinakumar Appuswamy, Michael Beyeler, Pallab Datta, Dharmendra S. Modha | 2023-04-25 |
| 11537859 | Flexible precision neural inference processing unit | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steve Esser +4 more | 2022-12-27 |
| 11514298 | High-frame-rate real-time multiscale spatiotemporal disparity on distributed low-power event-based neuromorphic hardware | Alexander Andreopoulos, Hirak Jyoti Kashyap | 2022-11-29 |
| 11501140 | Runtime reconfigurable neural network processor core | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Steven K. Esser +5 more | 2022-11-15 |
| 11301757 | Fault-tolerant power-driven synthesis | Charles J. Alpert, Pallab Datta, Zhou Li, Dharmendra S. Modha, Gi-Joon Nam | 2022-04-12 |
| 11270196 | Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine | Jun Sawada, Filipp A. Akopyan, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy +5 more | 2022-03-08 |
| 11263011 | Compound instruction set architecture for a neural inference chip | Andrew S. Cassidy, Rathinakumar Appuswamy, John V. Arthur, Pallab Datta, Michael Vincent DeBole +5 more | 2022-03-01 |
| 11238347 | Data distribution in an array of neural network cores | Brian Taba, Andrew S. Cassidy, Pallab Datta, Hartmut Penner, Rathinakumar Appuswamy +5 more | 2022-02-01 |
| 11205419 | Low energy deep-learning networks for generating auditory features for audio processing pipelines | Davis Barch, Andrew S. Cassidy | 2021-12-21 |
| 11200496 | Hardware-software co-design of neurosynaptic systems | John V. Arthur, Pallab Datta, Steven K. Esser, Dharmendra S. Modha, Tapan K. Nayak | 2021-12-14 |
| 11157795 | Graph partitioning and placement for multi-chip neurosynaptic networks | Arnon Amir, Pallab Datta, Dharmendra S. Modha, Tapan K. Nayak | 2021-10-26 |
| 11049000 | Distributed state via cascades of tensor decompositions and neuron activation binding on neuromorphic hardware | Alexander Andreopoulos | 2021-06-29 |
| 11010662 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2021-05-18 |
| 10832121 | Transform for a neurosynaptic core circuit | Rathinakumar Appuswamy, Dharmendra S. Modha | 2020-11-10 |
| 10832125 | Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm | Arnon Amir, Rathinakumar Appuswamy, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha +1 more | 2020-11-10 |