Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11966776 | Learning agent based application scheduling | Aporva Amarnath, Augusto J. Vega, Alper Buyuktosunoglu, Hubertus Franke, Pradip Bose | 2024-04-23 |
| 11740933 | Heterogeneous system on a chip scheduler with learning agent | Augusto J. Vega, Alper Buyuktosunoglu, Hubertus Franke, Pradip Bose, Robert M. Senger +1 more | 2023-08-29 |
| 11704155 | Heterogeneous system on a chip scheduler | Augusto J. Vega, Alper Buyuktosunoglu, Hubertus Franke, Pradip Bose, Robert M. Senger +1 more | 2023-07-18 |
| 11360772 | Instruction sequence merging and splitting for optimized accelerator implementation | Alper Buyuktosunoglu, David Trilla Rodriguez, Pradip Bose | 2022-06-14 |
| 9626293 | Single-thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi +4 more | 2017-04-18 |
| 9619385 | Single thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi +4 more | 2017-04-11 |
| 8918623 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2014-12-23 |
| 8893095 | Methods for generating code for an architecture encoding an extended register specification | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2014-11-18 |
| 8893079 | Methods for generating code for an architecture encoding an extended register specification | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2014-11-18 |
| 8589662 | Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals | Erik R. Altman, Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, Victor Zyuban | 2013-11-19 |
| 8312424 | Methods for generating code for an architecture encoding an extended register specification | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2012-11-13 |
| 8166281 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2012-04-24 |
| 8156310 | Method and apparatus for data stream alignment support | Alexandre E. Eichenberger, Michael K. Gschwind, Peng Wu | 2012-04-10 |
| 8151092 | Control signal memoization in a multiple instruction issue microprocessor | Erik R. Altman, Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, Victor Zyuban | 2012-04-03 |
| 8091050 | Modeling system-level effects of soft errors | Pradip Bose, Prabhakar Kudva, Jude A. Rivers, Pia Naoko Sanda | 2012-01-03 |
| 8000953 | Augmenting of automated clustering-based trace sampling methods by user-directed phase detection | Robert H. Bell, Jr., Wen-Tzer T. Chen, Pattabi R. Seshadri | 2011-08-16 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, David Arnold Luick, Daniel A. Prener, Jude A. Rivers +1 more | 2011-01-04 |
| 7793081 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2010-09-07 |
| 7509457 | Non-homogeneous multi-processor system with shared memory | Erik R. Altman, Peter G. Capek, Michael K. Gschwind, Charles Ray Johns, Harm Peter Hofstee +4 more | 2009-03-24 |
| 7496733 | System and method of execution of register pointer instructions ahead of instruction issues | Erik R. Altman, Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, Victor Zyuban | 2009-02-24 |
| 7461209 | Transient cache storage with discard function for disposable data | Erik R. Altman, Michael K. Gschwind, Robert K. Montoye, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2008-12-02 |
| 7454597 | Computer processing system employing an instruction schedule cache | Krishnan K. Kailas, Ravi Nair, Sumedh W. Sathaye, Wolfram Sauer | 2008-11-18 |
| 7421566 | Implementing instruction set architectures with non-contiguous register file specifiers | Michael K. Gschwind, Robert K. Montoye, Brett Olsson | 2008-09-02 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, David Arnold Luick, Daniel A. Prener, Jude A. Rivers +1 more | 2008-03-04 |
| 7325124 | System and method of execution of register pointer instructions ahead of instruction issue | Erik R. Altman, Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, Victor Zyuban | 2008-01-29 |