Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11295201 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2022-04-05 |
| 10810487 | Reconfigurable and customizable general-purpose circuits for neural networks | Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha +4 more | 2020-10-20 |
| 10628732 | Reconfigurable and customizable general-purpose circuits for neural networks | Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha +4 more | 2020-04-21 |
| 10331998 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2019-06-25 |
| 9818058 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | John V. Arthur, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2017-11-14 |
| 9460383 | Reconfigurable and customizable general-purpose circuits for neural networks | Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha +4 more | 2016-10-04 |
| 9373073 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | John V. Arthur, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2016-06-21 |
| 9239984 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Leland Chang, Daniel J. Friedman, Paul A. Merolla, Dharmendra S. Modha +3 more | 2016-01-19 |
| 8983992 | Facilitating field programmable gate array accelerations of database functions | Sameh W. Asaad, Donna N. Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min +2 more | 2015-03-17 |
| 8977637 | Facilitating field programmable gate array accelerations of database functions | Sameh W. Asaad, Donna N. Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min +2 more | 2015-03-10 |
| 8898097 | Reconfigurable and customizable general-purpose circuits for neural networks | Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha +4 more | 2014-11-25 |
| 8856055 | Reconfigurable and customizable general-purpose circuits for neural networks | Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha +4 more | 2014-10-07 |
| 8737233 | Increasing throughput of multiplexed electrical bus in pipe-lined architecture | Sameh W. Asaad, Mohit Kapur | 2014-05-27 |
| 8640070 | Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) | Sameh W. Asaad, Ralph E. Bellofatto, Charles L. Haymes, Mohit Kapur, Benjamin D. Parker +2 more | 2014-01-28 |
| 7382792 | Queue scheduling mechanism in a data packet transmission system | Alain Blanc, Rene Gallezot, Francois Le Mauf, Daniel Wind | 2008-06-03 |
| 7061909 | System and method for controlling the multicast traffic of a data packet switch | Alain Blanc, Rene Gallezot, Franco Le Maut, Thierry Roman, Daniel Wind | 2006-06-13 |
| 6992980 | System and method for enabling a full flow control down to the sub-ports of a switch fabric | Rene Gallezot, Francois Le Maut, Daniel Wind | 2006-01-31 |
| 6661786 | Service message system for a switching architecture | Jean-Claude Abbiate, Alain Blanc, Sylvie Gohl, Michel Poret | 2003-12-09 |
| 6606300 | Flow control process for a switching system and system for performing the same | Alain Blanc, Pierre Debord, Alain Saurel | 2003-08-12 |
| 6597656 | Switch system comprising two switch fabrics | Alain Blanc, Sylvie Gohl, Alain Saurel, Jean-Claude Robbe | 2003-07-22 |
| 6570845 | Switching system including a mask mechanism for altering the internal routing process | Alain Blanc, Alain Saurel | 2003-05-27 |
| 6452900 | Flow control process for a switching architecture using an out-of-band flow control channel and apparatus for performing the same | Alain Blanc, Pierre Debord, Albert X. Widmer | 2002-09-17 |
| 6343081 | Method and apparatus for managing contention in a self-routing switching architecture in a port expansion mode | Alain Blanc, Pierre Debord, Patrick Jeanniot, Alain Saurel | 2002-01-29 |
| 6108334 | Switching system comprising distributed elements allowing attachment to line adapters | Alain Blanc, Michel Poret, Alain Saurel | 2000-08-22 |
| 5341475 | Method for exchanging messages between a shared memory and communication adapters using an efficient logical protocol | Pierre Austruy, Jean-Pierre Lips, Bernard Naudin, Jean Calvignac, Richard H. Waller | 1994-08-23 |