Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7592933 | Techniques for 9B10B and 7B8B coding and decoding | — | 2009-09-22 |
| 7405679 | Techniques for 9B10B and 7B8B coding and decoding | — | 2008-07-29 |
| 7292161 | NB/MB coding apparatus and method using both disparity independent and disparity dependent encoded vectors | — | 2007-11-06 |
| 6977599 | 8B/10B encoding and decoding for high speed applications | — | 2005-12-20 |
| 6978416 | Error correction with low latency for bus structures | — | 2005-12-20 |
| 6911921 | 5B/6B-T, 3B/4B-T and partitioned 8B/10B-T and 10B/12B transmission codes, and their implementation for high operating rates | — | 2005-06-28 |
| 6876315 | DC-balanced 6B/8B transmission code with local parity | — | 2005-04-05 |
| 6614369 | DC balanced 7B/8B, 9B/10B, and partitioned DC balanced 12B/14B, 17B/20B, and 16B/18B transmission codes | — | 2003-09-02 |
| 6549310 | Fiber optic data link module with built-in link diagnostics | Daniel M. Kuchta | 2003-04-15 |
| 6496540 | Transformation of parallel interface into coded format with preservation of baud-rate | — | 2002-12-17 |
| 6452900 | Flow control process for a switching architecture using an out-of-band flow control channel and apparatus for performing the same | Alain Blanc, Bernard V. Brezzo, Pierre Debord | 2002-09-17 |
| 6429794 | Format converter | Charles L. Haymes, Benjamin D. Parker | 2002-08-06 |
| 6198413 | Partitioned DC balanced (0,6) 16B/18B transmission code with error correction | — | 2001-03-06 |
| 5784387 | Method for detecting start-of-frame, end of frame and idle words in a data stream | — | 1998-07-21 |
| 5740186 | Apparatus and method for error correction based on transmission code violations and parity | — | 1998-04-14 |
| 5699062 | Transmission code having local parity | — | 1997-12-16 |
| 5648776 | Serial-to-parallel converter using alternating latches and interleaving techniques | — | 1997-07-15 |
| 5457718 | Compact phase recovery scheme using digital circuits | Carl J. Anderson, Kevin R. Wrenner | 1995-10-10 |
| 5301196 | Half-speed clock recovery and demultiplexer circuit | John F. Ewen | 1994-04-05 |
| 4665517 | Method of coding to minimize delay at a communication node | — | 1987-05-12 |
| 4486739 | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code | Peter A. Franaszek | 1984-12-04 |
| 4408167 | Current amplifier stage with diode interstage connection | Dennis L. Rogers | 1983-10-04 |