Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12287829 | Minimizing hash collisions of composite keys | Bharat Sukhwani, Sameh W. Asaad | 2025-04-29 |
| 12061521 | Non-blocking hardware function request retries to address response latency variabilities | Bharat Sukhwani, Sameh W. Asaad | 2024-08-13 |
| 11907361 | System and method for supporting secure objects using a memory access control monitor | Richard H. Boivie, Kattamuri Ekanadham, Kenneth A. Goldman, William E. Hall, Guerney D. H. Hunt +5 more | 2024-02-20 |
| 11093674 | Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator | Sameh W. Asaad | 2021-08-17 |
| 11047907 | Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator | Sameh W. Asaad | 2021-06-29 |
| 10924193 | Transmit and receive radio frequency (RF) signals without the use of baseband generators and local oscillators for up conversion and down conversion | Muir Kumph | 2021-02-16 |
| 10904226 | Secure processing environment for protecting sensitive information | Richard H. Boivie, Alyson Comer, John C. Dayka, Donna N. Dillenberger, Kenneth A. Goldman +4 more | 2021-01-26 |
| 10705556 | Phase continuous signal generation using direct digital synthesis | Muir Kumph, Jiri Stehlik | 2020-07-07 |
| 10628579 | System and method for supporting secure objects using a memory access control monitor | Richard H. Boivie, Kattamuri Ekanadham, Kenneth A. Goldman, William E. Hall, Guerney Douglass Holloway Hunt +5 more | 2020-04-21 |
| 10547596 | Secure processing environment for protecting sensitive information | Richard H. Boivie, Alyson Comer, John C. Dayka, Donna N. Dillenberger, Kenneth A. Goldman +4 more | 2020-01-28 |
| 10523640 | Secure processing environment for protecting sensitive information | Richard H. Boivie, Alyson Comer, John C. Dayka, Donna N. Dillenberger, Kenneth A. Goldman +4 more | 2019-12-31 |
| 10488460 | Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator | Sameh W. Asaad | 2019-11-26 |
| 10298545 | Secure processing environment for protecting sensitive information | Richard H. Boivie, Alyson Comer, John C. Dayka, Donna N. Dillenberger, Kenneth A. Goldman +4 more | 2019-05-21 |
| 10176281 | Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator | Sameh W. Asaad | 2019-01-08 |
| 10158607 | Secure processing environment for protecting sensitive information | Richard H. Boivie, Alyson Comer, John C. Dayka, Donna N. Dillenberger, Kenneth A. Goldman +4 more | 2018-12-18 |
| 9286423 | Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator | Sameh W. Asaad | 2016-03-15 |
| 9230046 | Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator | Sameth W. Asaad | 2016-01-05 |
| 9002693 | Wire like link for cycle reproducible and cycle accurate hardware accelerator | Sameh W. Asaad, Benjamin D. Parker | 2015-04-07 |
| 8737233 | Increasing throughput of multiplexed electrical bus in pipe-lined architecture | Sameh W. Asaad, Bernard V. Brezzo | 2014-05-27 |
| 8640070 | Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) | Sameh W. Asaad, Ralph E. Bellofatto, Bernard V. Brezzo, Charles L. Haymes, Benjamin D. Parker +2 more | 2014-01-28 |
| 7757142 | Self-synchronizing pseudorandom bit sequence checker | Seongwon Kim | 2010-07-13 |
| 7724059 | Clock scaling circuit | — | 2010-05-25 |
| 7509568 | Error type identification circuit for identifying different types of errors in communications devices | Jose A. Tierno | 2009-03-24 |
| 7412640 | Self-synchronizing pseudorandom bit sequence checker | Seongwon Kim | 2008-08-12 |
| 7177775 | Testable digital delay line | Seongwon Kim | 2007-02-13 |