Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10219556 | Actively controlled performance clothing | David Joel Edelsohn, Kaoutar El Maghraoui, Jose E. Moreira, Priya Ashok Nagpurkar, Jessica Hui-Chun Tseng | 2019-03-05 |
| 10055295 | Using spare capacity in solid state drives | Diyanesh B. Chinnakkonda Vidyapoornachary, Gary A. Tressler | 2018-08-21 |
| 9928158 | Redundant transactions for detection of timing sensitive errors | Harold W. Cain, III, Michael C. Huang, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano | 2018-03-27 |
| 9842050 | Add-on memory coherence directory | — | 2017-12-12 |
| 9836398 | Add-on memory coherence directory | — | 2017-12-05 |
| 9792209 | Method and apparatus for cache memory data processing | Edgar R. Cordero, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary | 2017-10-17 |
| 9766937 | Thread-based cache content saving for task switching | Harold W. Cain, III, Brian R. Prasky, Vijayalakshmi Srinivasan | 2017-09-19 |
| 9760490 | Private memory table for reduced memory coherence traffic | Vijayalakshmi Srinivasan | 2017-09-12 |
| 9760133 | Locking power supplies | Harold W. Cain, III, Jose E. Moreira | 2017-09-12 |
| 9760489 | Private memory table for reduced memory coherence traffic | Vijayalakshmi Srinivasan | 2017-09-12 |
| 9710381 | Method and apparatus for cache memory data processing | Edgar R. Cordero, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary | 2017-07-18 |
| 9697128 | Prefetch threshold for cache restoration | Harold W. Cain, III, Brian R. Prasky, Vijayalakshmi Srinivasan | 2017-07-04 |
| 9619356 | Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor | Harold W. Cain, III, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2017-04-11 |
| 9495248 | Using spare capacity in solid state drives | Diyanesh B. Chinnakkonda Vidyapoornachary, Gary A. Tressler | 2016-11-15 |
| 9471428 | Using spare capacity in solid state drives | Diyanesh B. Chinnakkonda Vidyapoornachary, Gary A. Tressler | 2016-10-18 |
| 9459979 | Detection of hardware errors using redundant transactions for system test | Harold W. Cain, III, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2016-10-04 |
| 9448835 | Thread-based cache content saving for task switching | Harold W. Cain, III, Brian R. Prasky, Vijayalakshmi Srinivasan | 2016-09-20 |
| 9436501 | Thread-based cache content saving for task switching | Harold W. Cain, III, Brian R. Prasky, Vijayalakshmi Srinivasan | 2016-09-06 |
| 9424192 | Private memory table for reduced memory coherence traffic | Vijayalakshmi Srinivasan | 2016-08-23 |
| 9411730 | Private memory table for reduced memory coherence traffic | Vijayalakshmi Srinivasan | 2016-08-09 |
| 9311228 | Power reduction in server memory system | Tejas Karkhanis, Valentina Salapura | 2016-04-12 |
| 9304863 | Transactions for checkpointing and reverse execution | Harold W. Cain, III, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano | 2016-04-05 |
| 9256752 | Product authorization with cross-region access | Davor Golac, Myron Wan, Larry Leach, Sunil Bhalla | 2016-02-09 |
| 9251014 | Redundant transactions for detection of timing sensitive errors | Harold W. Cain, III, Michael C. Huang, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano | 2016-02-02 |
| 8930625 | Weighted history allocation predictor algorithm in a hybrid cache | Benjiman L. Goodman, Stephen J. Powell, Aaron C. Sawdey, Jeffrey A. Stuecheli | 2015-01-06 |