TK

Tejas Karkhanis

IBM: 12 patents #9,222 of 70,183Top 15%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Overall (All Time): #346,082 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11210092 Servicing indirect data storage requests with multiple memory controllers Philip G. Emma, Michael B. Healy, Ching-Pei Lin 2021-12-28
10795683 Predicting indirect branches using problem branch filtering and pattern cache Richard J. Eickemeyer, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan, Mauricio J. Serrano 2020-10-06
10776155 Aggregating, disaggregating and converting electronic transaction request messages Philip G. Emma, Michael B. Healy, Ching-Pei Lin 2020-09-15
10740003 Latency-agnostic memory controller Philip G. Emma, Michael B. Healy 2020-08-11
10613774 Partitioned memory with locally aggregated copy pools Philip G. Emma, Michael B. Healy, Ching-Pei Lin 2020-04-07
10606487 Partitioned memory with locally aggregated copy pools Philip G. Emma, Michael B. Healy, Ching-Pei Lin 2020-03-31
9524166 Tracking long GHV in high performance out-of-order superscalar processors Richard J. Eickemeyer, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan, Jose E. Moreira +1 more 2016-12-20
9483271 Compressed indirect prediction caches David S. Levitan, Jose E. Moreira, Mauricio J. Serrano 2016-11-01
9442736 Techniques for selecting a predicted indirect branch address from global and local caches Richard J. Eickemeyer, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan 2016-09-13
9311228 Power reduction in server memory system David M. Daly, Valentina Salapura 2016-04-12
8892921 Power management for systems on a chip Chen-Yong Cher, Srinivasan Ramani 2014-11-18
8312305 Power management for systems on a chip Chen-Yong Cher, Srinivasan Ramani 2012-11-13
7818696 Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores Pradip Bose, Srinivasan Ramani, Malcolm S. Ware, Ken V. Vu 2010-10-19
7249331 Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores Pradip Bose, Srinivasan Ramani, Malcolm S. Ware, Ken V. Vu 2007-07-24