Issued Patents All Time
Showing 25 most recent of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12164921 | Comparing hash values computed at function entry and exit for increased security | Arnold Flores, Debapriya Chatterjee, Kattamuri Ekanadham | 2024-12-10 |
| 12061910 | Dispatching multiply and accumulate operations based on accumulator register index number | Jentje Leenstra, Andreas Wagner, Brian W. Thompto | 2024-08-13 |
| 12008149 | Method and system for on demand control of hardware support for software pointer authentification in a computing system | Debapriya Chatterjee, Brian W. Thompto | 2024-06-11 |
| 12008150 | Encrypted data processing design including cleartext register files | Jessica Hui-Chun Tseng, Pratap C. Pattnaik, Manoj Kumar, Kattamuri Ekanadham, Gianfranco Bilardi | 2024-06-11 |
| 11900116 | Loosely-coupled slice target file data | Dung Q. Nguyen, Brian W. Thompto, Jessica Hui-Chun Tseng, Pratap C. Pattnaik, Kattamuri Ekanadham +1 more | 2024-02-13 |
| 11868275 | Encrypted data processing design including local buffers | Manoj Kumar, Gianfranco Bilardi, Kattamuri Ekanadham, Pratap C. Pattnaik, Jessica Hui-Chun Tseng | 2024-01-09 |
| 11836493 | Memory access operations for large graph analytics | Manoj Kumar, Gianfranco Bilardi, Kattamuri Ekanadham, Pratap C. Pattnaik, Jessica Hui-Chun Tseng | 2023-12-05 |
| 11755320 | Compute array of a processor with mixed-precision numerical linear algebra support | Brett Olsson, Brian W. Thompto, Silvia M. Mueller, Andreas Wagner | 2023-09-12 |
| 11755325 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Hung Q. Le, Silvia M. Mueller +1 more | 2023-09-12 |
| 11663009 | Supporting large-word operations in a reduced instruction set computer (“RISC”) processor | Sandhya Koteshwara, Kattamuri Ekanadham, Manoj Kumar, Pratap C. Pattnaik | 2023-05-30 |
| 11294685 | Instruction fusion using dependence analysis | Jessica Hui-Chun Tseng, Manoj Kumar, Kattamuri Ekanadham, Pratap C. Pattnaik | 2022-04-05 |
| 11281745 | Half-precision floating-point arrays at low overhead | Bruce M. Fleischer, Joel A. Silberman | 2022-03-22 |
| 11188328 | Compute array of a processor with mixed-precision numerical linear algebra support | Brett Olsson, Brian W. Thompto, Silvia M. Mueller, Andreas Wagner | 2021-11-30 |
| 11182458 | Three-dimensional lane predication for matrix operations | Brett Olsson, Brian W. Thompto, Silvia M. Mueller, Andreas Wagner | 2021-11-23 |
| 11163528 | Reformatting matrices to improve computing efficiency | Manoj Kumar, Pratap C. Pattnaik, Kattamuri Ekanadham, Jessica Hui-Chun Tseng | 2021-11-02 |
| 11144323 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +1 more | 2021-10-12 |
| 11132198 | Instruction handling for accumulation of register results in a microprocessor | Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Hung Q. Le, Silvia M. Mueller +1 more | 2021-09-28 |
| 10983800 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Bruce Joseph Ronchetti, Brian W. Thompto +1 more | 2021-04-20 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Dung Q. Nguyen, Hung Q. Le +3 more | 2021-04-20 |
| 10956361 | Processor core design optimized for machine learning applications | Manoj Kumar, Pratap C. Pattnaik, Kattamuri Ekanadham, Jessica Hui-Chun Tseng | 2021-03-23 |
| 10956167 | Mechanism for instruction fusion using tags | Jessica Hui-Chun Tseng, Manoj Kumar, Kattamuri Ekanadham, Pratap C. Pattnaik | 2021-03-23 |
| 10936323 | Optimize control-flow convergence on SIMD engine using divergence depth | Gheorghe Almasi, Jessica Hui-Chun Tseng, Peng Wu | 2021-03-02 |
| 10936320 | Efficient performance of inner loops on a multi-lane processor | Kattamuri Ekanadham, Manoj Kumar, Pratap C. Pattnaik, Jessica Hui-Chun Tseng | 2021-03-02 |
| 10884942 | Reducing memory access latency in scatter/gather operations | William P. Horn, Joefon Jann, Manoj Kumar, Pratap C. Pattnaik, Mauricio J. Serrano +1 more | 2021-01-05 |
| 10691459 | Converting multiple instructions into a single combined instruction with an extension opcode | Giles R. Frazier, Hung Q. Le, Brian W. Thompto | 2020-06-23 |