Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10983800 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2021-04-20 |
| 10157064 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2018-12-18 |
| 10083039 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2018-09-25 |
| 9977678 | Reconfigurable parallel execution and load-store slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2018-05-22 |
| 9971602 | Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2018-05-15 |
| 9690585 | Parallel slice processor with dynamic instruction stream mapping | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2017-06-27 |
| 9690586 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2017-06-27 |
| 9672043 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2017-06-06 |
| 9665372 | Parallel slice processor with dynamic instruction stream mapping | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Brian W. Thompto +1 more | 2017-05-30 |
| 8271765 | Managing instructions for more efficient load/store unit usage | Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Dung Q. Nguyen | 2012-09-18 |
| 8156287 | Adaptive data prefetch | Pradip Bose, Alper Buyuktosunoglu, Miles Robert Dooley, Michael Stephen Floyd, David Scott Ray | 2012-04-10 |
| 8086801 | Loading data to vector renamed register from across multiple cache lines | David A. Hrusecky, David Scott Ray, Shih-Hsiung S. Tung | 2011-12-27 |
| 7752354 | Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor | Miles Robert Dooley, Joaquin Hinojosa, Anthony Saporito | 2010-07-06 |
| 7660965 | Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream | Joaquin Hinojosa, Sheldon B. Levenstein | 2010-02-09 |
| 7571283 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch | Scott Bruce Frommer, Sheldon B. Levenstein, Anthony Saporito | 2009-08-04 |
| 7380062 | Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch | Scott Bruce Frommer, Sheldon B. Levenstein, Anthony Saporito | 2008-05-27 |
| 7350051 | Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream | Joaquin Hinojosa, Sheldon B. Levenstein | 2008-03-25 |
| 7318127 | Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor | David A. Hrusecky, Sheldon B. Levenstein, Anthony Saporito | 2008-01-08 |
| 7284094 | Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class | David A. Hrusecky, Sheldon B. Levenstein, Anthony Saporito | 2007-10-16 |
| 6981128 | Atomic quad word storage in a simultaneous multithreaded system | Eric Jason Fluhr, Joaquin Hinojosa, Ronald Nick Kalla, Balaram Sinharoy | 2005-12-27 |
| 6640293 | Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays | Jose Angel Paredes, Binta M. Patel, George McNeil Lattimore | 2003-10-28 |
| 6490653 | Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system | Robert Alan Cargnoni, David Shippy, Larry Edward Thatcher | 2002-12-03 |
| 6484230 | Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction | Brian R. Konigsburg, Alexander Edward Okpisz, Thomas A. Petersen | 2002-11-19 |
| 6349382 | System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order | Kurt A. Feiste, David Shippy | 2002-02-19 |
| 6336168 | System and method for merging multiple outstanding load miss instructions | Marlin Wayne Frederick, Jr., David Shippy, Larry Edward Thatcher | 2002-01-01 |