Issued Patents All Time
Showing 25 most recent of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11687369 | Flexible optimized data handling in systems with multiple memories | Tong Chen, Daniel A. Prener, Zehra N. Sura | 2023-06-27 |
| 10996989 | Flexible optimized data handling in systems with multiple memories | Tong Chen, Daniel A. Prener, Zehra N. Sura | 2021-05-04 |
| 10782973 | Optimizing branch re-wiring in a software instruction cache | Carlo Bertolli, Alexandre E. Eichenberger, Zehra N. Sura | 2020-09-22 |
| 10324694 | Arranging binary code based on call graph partitioning | Tong Chen, Brian Flachs, Brad W. Michael, Mark Richard Nutter, Kathryn M. O'Brien +1 more | 2019-06-18 |
| 10223260 | Compiler-generated memory mapping hints | Kathryn M. O'Brien, Zehra N. Sura | 2019-03-05 |
| 10223091 | Unaligned instruction relocation | Carlo Bertolli, Olivier H. Sallenave, Zehra N. Sura | 2019-03-05 |
| 10169013 | Arranging binary code based on call graph partitioning | Tong Chen, Brian Flachs, Brad W. Michael, Mark Richard Nutter, Kathryn M. O'Brien +1 more | 2019-01-01 |
| 10083125 | Method to efficiently implement synchronization using software managed address translation | Tong Chen, Zehra N. Sura | 2018-09-25 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9916144 | Arranging binary code based on call graph partitioning | Tong Chen, Brian Flachs, Brad W. Michael, Mark Richard Nutter, Kathryn M. O'Brien +1 more | 2018-03-13 |
| 9875089 | Unaligned instruction relocation | Carlo Bertolli, Olivier H. Sallenave, Zehra N. Sura | 2018-01-23 |
| 9792098 | Unaligned instruction relocation | Carlo Bertolli, Olivier H. Sallenave, Zehra N. Sura | 2017-10-17 |
| 9772825 | Program structure-based blocking | Carlo Bertolli, Alexandre E. Eichenberger, Zehra N. Sura | 2017-09-26 |
| 9772824 | Program structure-based blocking | Carlo Bertolli, Alexandre E. Eichenberger, Zehra N. Sura | 2017-09-26 |
| 9658940 | Method to efficiently implement synchronization using software managed address translation | Tong Chen, Zehra N. Sura | 2017-05-23 |
| 9600253 | Arranging binary code based on call graph partitioning | Tong Chen, Brian Flachs, Brad W. Michael, Mark Richard Nutter, Kathryn M. O'Brien +1 more | 2017-03-21 |
| 9519583 | Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute | George Liang-Tai Chiu, Alexandre E. Eichenberger | 2016-12-13 |
| 9513832 | Accessing global data from accelerator devices | Carlo Bertolli, Olivier H. Sallenave, Zehra N. Sura | 2016-12-06 |
| 9513828 | Accessing global data from accelerator devices | Carlo Bertolli, Olivier H. Sallenave, Zehra N. Sura | 2016-12-06 |
| 9459851 | Arranging binary code based on call graph partitioning | Tong Chen, Brian Flachs, Brad W. Michael, Mark Richard Nutter, Kathryn M. O'Brien +1 more | 2016-10-04 |
| 9229715 | Method and apparatus for efficient inter-thread synchronization for helper threads | Michael K. Gschwind, Valentina Salapura, Zehra N. Sura | 2016-01-05 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +55 more | 2015-07-14 |
| 9043194 | Method and system for efficient emulation of multiprocessor memory consistency | Ravi Nair, Kathryn M. O'Brien, Peter Howland Oden, Daniel A. Prener | 2015-05-26 |
| 9038040 | Method for partitioning programs between a general purpose core and one or more accelerators | Kathryn M. O'Brien, Daniel A. Prener | 2015-05-19 |
| 8997071 | Optimized division of work among processors in a heterogeneous processing system | Tong Chen, Zehra N. Sura | 2015-03-31 |